From f1c9c1ebc0659c93e457a93fd44a3e38d2183641 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Tue, 12 Mar 2019 15:39:27 -0700 Subject: [PATCH] gpu: nvgpu: remove unused register and fields cleanup header for removal of czf_bypass and pd_max_batches support. JIRA NVGPU-2967 Change-Id: I7a1d8dfeabb87e3653c70a560282f99ff4310ce7 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2071070 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 22 +------------------ 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h index e1e739eaa..e531e5f19 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1734,10 +1734,6 @@ static inline u32 gr_pd_ab_dist_cfg1_r(void) { return 0x004064c4U; } -static inline u32 gr_pd_ab_dist_cfg1_max_batches_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) { return 0xffffU; @@ -4398,20 +4394,4 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { return U32(0xffU) << 0U; } -static inline u32 gr_gpc0_prop_debug1_r(void) -{ - return 0x00500400U; -} -static inline u32 gr_gpc0_prop_debug1_czf_bypass_f(u32 v) -{ - return (v & 0x3U) << 14U; -} -static inline u32 gr_gpc0_prop_debug1_czf_bypass_m(void) -{ - return U32(0x3U) << 14U; -} -static inline u32 gr_gpc0_prop_debug1_czf_bypass_init_v(void) -{ - return 0x00000001U; -} #endif