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gpu: nvgpu: remove channel cycle stats ioctls

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Cycle stats and cycle stats snapshot ioctls have been moved to
debug node. Removing channel ioctls.

Bug 220464613

Change-Id: I3aecdf4a8310eeb38de2de5ac076048891afe436
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030992
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-02-28 15:01:09 -08:00
committed by mobile promotions
parent 3dca832142
commit f20424ea6a
3 changed files with 4 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/include/nvgpu/enabled.h
View File

@@ -91,9 +91,9 @@ struct gk20a;
#define NVGPU_HAS_SYNCPOINTS 30 #define NVGPU_HAS_SYNCPOINTS 30
/* sync fence FDs are available in, e.g., submit_gpfifo */ /* sync fence FDs are available in, e.g., submit_gpfifo */
#define NVGPU_SUPPORT_SYNC_FENCE_FDS 31 #define NVGPU_SUPPORT_SYNC_FENCE_FDS 31
/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */
#define NVGPU_SUPPORT_CYCLE_STATS 32 #define NVGPU_SUPPORT_CYCLE_STATS 32
/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */
#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33 #define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33
/* Both gpu driver and device support TSG */ /* Both gpu driver and device support TSG */
#define NVGPU_SUPPORT_TSG 34 #define NVGPU_SUPPORT_TSG 34

69
drivers/gpu/nvgpu/os/linux/ioctl_channel.c
View File

@@ -278,47 +278,6 @@ int gk20a_channel_free_cycle_stats_snapshot(struct channel_gk20a *ch)
return ret; return ret;
} }
static int gk20a_channel_cycle_stats_snapshot(struct channel_gk20a *ch,
struct nvgpu_cycle_stats_snapshot_args *args)
{
int ret;
/* is it allowed to handle calls for current GPU? */
if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT))
return -ENOSYS;
if (!args->dmabuf_fd)
return -EINVAL;
nvgpu_speculation_barrier();
/* handle the command (most frequent cases first) */
switch (args->cmd) {
case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH:
ret = gk20a_flush_cycle_stats_snapshot(ch);
args->extra = 0;
break;
case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH:
ret = gk20a_attach_cycle_stats_snapshot(ch,
args->dmabuf_fd,
args->extra,
&args->extra);
break;
case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH:
ret = gk20a_channel_free_cycle_stats_snapshot(ch);
args->extra = 0;
break;
default:
pr_err("cyclestats: unknown command %u\n", args->cmd);
ret = -EINVAL;
break;
}
return ret;
}
#endif #endif
static int gk20a_channel_set_wdt_status(struct channel_gk20a *ch, static int gk20a_channel_set_wdt_status(struct channel_gk20a *ch,
@@ -1278,20 +1237,6 @@ long gk20a_channel_ioctl(struct file *filp,
(struct nvgpu_set_error_notifier *)buf); (struct nvgpu_set_error_notifier *)buf);
gk20a_idle(ch->g); gk20a_idle(ch->g);
break; break;
#ifdef CONFIG_GK20A_CYCLE_STATS
case NVGPU_IOCTL_CHANNEL_CYCLE_STATS:
err = gk20a_busy(ch->g);
if (err) {
dev_err(dev,
"%s: failed to host gk20a for ioctl cmd: 0x%x",
__func__, cmd);
break;
}
err = gk20a_channel_cycle_stats(ch,
((struct nvgpu_cycle_stats_args *)buf)->dmabuf_fd);
gk20a_idle(ch->g);
break;
#endif
case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT: case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT:
{ {
u32 timeout = u32 timeout =
@@ -1394,20 +1339,6 @@ long gk20a_channel_ioctl(struct file *filp,
NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR, true); NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR, true);
gk20a_idle(ch->g); gk20a_idle(ch->g);
break; break;
#ifdef CONFIG_GK20A_CYCLE_STATS
case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT:
err = gk20a_busy(ch->g);
if (err) {
dev_err(dev,
"%s: failed to host gk20a for ioctl cmd: 0x%x",
__func__, cmd);
break;
}
err = gk20a_channel_cycle_stats_snapshot(ch,
(struct nvgpu_cycle_stats_snapshot_args *)buf);
gk20a_idle(ch->g);
break;
#endif
case NVGPU_IOCTL_CHANNEL_WDT: case NVGPU_IOCTL_CHANNEL_WDT:
err = gk20a_channel_set_wdt_status(ch, err = gk20a_channel_set_wdt_status(ch,
(struct nvgpu_channel_wdt_args *)buf); (struct nvgpu_channel_wdt_args *)buf);

27
include/uapi/linux/nvgpu.h
View File

@@ -114,9 +114,9 @@ struct nvgpu_gpu_zbc_query_table_args {
#define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1ULL << 2) #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1ULL << 2)
/* sync fence FDs are available in, e.g., submit_gpfifo */ /* sync fence FDs are available in, e.g., submit_gpfifo */
#define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1ULL << 3) #define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1ULL << 3)
/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */
#define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1ULL << 4) #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1ULL << 4)
/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ /* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */
#define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT (1ULL << 6) #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT (1ULL << 6)
/* User-space managed address spaces support */ /* User-space managed address spaces support */
#define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS (1ULL << 7) #define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS (1ULL << 7)
@@ -1618,11 +1618,6 @@ struct nvgpu_wait_args {
} condition; /* determined by type field */ } condition; /* determined by type field */
}; };
/* cycle stats support */
struct nvgpu_cycle_stats_args {
__u32 dmabuf_fd;
} __packed;
struct nvgpu_set_timeout_args { struct nvgpu_set_timeout_args {
__u32 timeout; __u32 timeout;
} __packed; } __packed;
@@ -1671,20 +1666,6 @@ struct nvgpu_notification {
#define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 #define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1
}; };
/* cycle stats snapshot buffer support for mode E */
struct nvgpu_cycle_stats_snapshot_args {
__u32 cmd; /* in: command to handle */
__u32 dmabuf_fd; /* in: dma buffer handler */
__u32 extra; /* in/out: extra payload e.g.*/
/* counter/start perfmon */
__u32 pad0[1];
};
/* valid commands to control cycle stats shared buffer */
#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH 0
#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH 1
#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH 2
/* configure watchdog per-channel */ /* configure watchdog per-channel */
struct nvgpu_channel_wdt_args { struct nvgpu_channel_wdt_args {
__u32 wdt_status; __u32 wdt_status;
@@ -1783,8 +1764,6 @@ struct nvgpu_reschedule_runlist_args {
_IOW(NVGPU_IOCTL_MAGIC, 100, struct nvgpu_alloc_gpfifo_args) _IOW(NVGPU_IOCTL_MAGIC, 100, struct nvgpu_alloc_gpfifo_args)
#define NVGPU_IOCTL_CHANNEL_WAIT \ #define NVGPU_IOCTL_CHANNEL_WAIT \
_IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args) _IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args)
#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS \
_IOWR(NVGPU_IOCTL_MAGIC, 106, struct nvgpu_cycle_stats_args)
#define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO \ #define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO \
_IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args) _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args)
#define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \ #define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \
@@ -1805,8 +1784,6 @@ struct nvgpu_reschedule_runlist_args {
_IO(NVGPU_IOCTL_MAGIC, 116) _IO(NVGPU_IOCTL_MAGIC, 116)
#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \ #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \
_IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args) _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args)
#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT \
_IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args)
#define NVGPU_IOCTL_CHANNEL_WDT \ #define NVGPU_IOCTL_CHANNEL_WDT \
_IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args)
#define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \