diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d579ad989..66f184471 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2449,7 +2449,8 @@ static void gr_gk20a_free_global_ctx_buffers(struct gk20a *g) int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; - int attr_buffer_size, err; + int err; + u32 attr_buffer_size; u32 cb_buffer_size = gr->bundle_cb_default_size * gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); @@ -2495,7 +2496,7 @@ int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) } } - nvgpu_log_info(g, "attr_buffer_size : %d", attr_buffer_size); + nvgpu_log_info(g, "attr_buffer_size : %u", attr_buffer_size); err = gk20a_gr_alloc_ctx_buffer(g, &gr->global_ctx_buffer[ATTRIBUTE], attr_buffer_size); diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index b7b4345e4..85b37e1be 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -97,10 +97,10 @@ void gr_gm20b_cb_size_default(struct gk20a *g) gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); } -int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) +u32 gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; - int size; + u32 size; gr->attrib_cb_size = gr->attrib_cb_default_size + (gr->attrib_cb_default_size >> 1); diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index b1c65159b..e0c001dac 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -55,7 +55,7 @@ void gm20a_gr_disable_rd_coalesce(struct gk20a *g); void gr_gm20b_init_gpc_mmu(struct gk20a *g); void gr_gm20b_bundle_cb_defaults(struct gk20a *g); void gr_gm20b_cb_size_default(struct gk20a *g); -int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g); +u32 gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g); void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, struct nvgpu_gr_ctx *ch_ctx, u64 addr, u64 size, bool patch); diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index 23dec6c0a..a85e09df6 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c @@ -31,13 +31,13 @@ #include void gm20b_mm_set_big_page_size(struct gk20a *g, - struct nvgpu_mem *mem, int size) + struct nvgpu_mem *mem, u32 size) { u32 val; nvgpu_log_fn(g, " "); - nvgpu_log_info(g, "big page size %d\n", size); + nvgpu_log_info(g, "big page size %u\n", size); val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w()); val &= ~ram_in_big_page_size_m(); diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h index be10be383..bb7783a0f 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h @@ -28,7 +28,7 @@ struct gk20a; #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) void gm20b_mm_set_big_page_size(struct gk20a *g, - struct nvgpu_mem *mem, int size); + struct nvgpu_mem *mem, u32 size); u32 gm20b_mm_get_big_page_sizes(void); u32 gm20b_mm_get_default_big_page_size(void); bool gm20b_mm_support_sparse(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 07c13a5cc..217b7b143 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -583,10 +583,10 @@ u32 gr_gp10b_pagepool_default_size(struct gk20a *g) return gr_scc_pagepool_total_pages_hwmax_value_v(); } -int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) +u32 gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; - int size; + u32 size; gr->attrib_cb_size = gr->attrib_cb_default_size; gr->alpha_cb_size = gr->alpha_cb_default_size; @@ -1479,10 +1479,10 @@ void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u64 addr, bool patch) { - int attrBufferSize; + u32 attrBufferSize; if (gr_ctx->preempt_ctxsw_buffer.gpu_va != 0ULL) { - attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; + attrBufferSize = U32(gr_ctx->betacb_ctxsw_buffer.size); } else { attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index ca9a0ff7c..382c009bd 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -88,7 +88,7 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index); u32 gr_gp10b_pagepool_default_size(struct gk20a *g); -int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g); +u32 gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g); void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data); void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data); int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index e6a220d45..9b996f3eb 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1164,10 +1164,10 @@ u32 gr_gv11b_pagepool_default_size(struct gk20a *g) return gr_scc_pagepool_total_pages_hwmax_value_v(); } -int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) +u32 gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; - int size; + u32 size; gr->attrib_cb_size = gr->attrib_cb_default_size; gr->alpha_cb_size = gr->alpha_cb_default_size; @@ -2070,10 +2070,10 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u64 addr, bool patch) { - int attrBufferSize; + u32 attrBufferSize; if (gr_ctx->preempt_ctxsw_buffer.gpu_va != 0ULL) { - attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; + attrBufferSize = U32(gr_ctx->betacb_ctxsw_buffer.size); } else { attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b46fe2a24..9c4134faa 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -121,7 +121,7 @@ int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, struct gr_gk20a *gr); int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr); u32 gr_gv11b_pagepool_default_size(struct gk20a *g); -int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g); +u32 gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g); int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data); void gr_gv11b_bundle_cb_defaults(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 853c497db..4d1e09ada 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -234,7 +234,7 @@ struct gpu_ops { void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset); void (*bundle_cb_defaults)(struct gk20a *g); void (*cb_size_default)(struct gk20a *g); - int (*calc_global_ctx_buffer_size)(struct gk20a *g); + u32 (*calc_global_ctx_buffer_size)(struct gk20a *g); void (*commit_global_attrib_cb)(struct gk20a *g, struct nvgpu_gr_ctx *ch_ctx, u64 addr, bool patch); @@ -976,7 +976,7 @@ struct gpu_ops { void (*l2_flush)(struct gk20a *g, bool invalidate); void (*cbc_clean)(struct gk20a *g); void (*set_big_page_size)(struct gk20a *g, - struct nvgpu_mem *mem, int size); + struct nvgpu_mem *mem, u32 size); u32 (*get_big_page_sizes)(void); u32 (*get_default_big_page_size)(void); u32 (*get_iommu_bit)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 6c1e17aca..7f5aed81f 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c @@ -133,7 +133,7 @@ int vgpu_gr_init_ctx_state(struct gk20a *g) static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; - int attr_buffer_size; + u32 attr_buffer_size; u32 cb_buffer_size = gr->bundle_cb_default_size * gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); @@ -151,7 +151,7 @@ static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g) nvgpu_log_info(g, "pagepool_buffer_size : %d", pagepool_buffer_size); gr->global_ctx_buffer[PAGEPOOL].mem.size = pagepool_buffer_size; - nvgpu_log_info(g, "attr_buffer_size : %d", attr_buffer_size); + nvgpu_log_info(g, "attr_buffer_size : %u", attr_buffer_size); gr->global_ctx_buffer[ATTRIBUTE].mem.size = attr_buffer_size; nvgpu_log_info(g, "priv access map size : %d",