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gpu: nvgpu: fix syncpt increment logic in host1x syncpt_set_minval

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On host copy engine PBDMA interrupt, channel is aborted as part of the
recovery and its syncpt value is set to the max threshold.

Syncpoint may then get incremented by PBDMA (incr cmd gets processed)
after this interrupt is handled leading to syncpoint value becoming
greater than the max threshold.

Again while unbinding the channel, syncpoint value is incremented until
it reaches max threshold. Since syncpoint value is already greater than
max threshold, host1x version of nvgpu_nvhost_syncpt_set_minval will
loop for entire u32 range until it reaches max threshold and this
will hang the channel unbind.

nvgpu_nvhost_syncpt_set_minval can ensure the syncpoint value is greater
than or equal to max threshold. Hence update the check for syncpoint
value from not equal to less than.

Bug 3681100

Change-Id: I96e7a1f53d4037e9ed858a2e90dd5a8d17ed6bb0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2742604
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2022-07-10 13:03:25 +05:30
committed by mobile promotions
parent da632aa173
commit f246facd01
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/nvgpu/os/linux/nvhost_host1x.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -193,9 +193,10 @@ void nvgpu_nvhost_syncpt_set_minval(struct nvgpu_nvhost_dev *nvhost_dev,
cur = host1x_syncpt_read(sp); cur = host1x_syncpt_read(sp);
while (cur++ != val) while (cur++ < val) {
host1x_syncpt_incr(sp); host1x_syncpt_incr(sp);
} }
}
void nvgpu_nvhost_syncpt_put_ref_ext(struct nvgpu_nvhost_dev *nvhost_dev, void nvgpu_nvhost_syncpt_put_ref_ext(struct nvgpu_nvhost_dev *nvhost_dev,
u32 id) u32 id)