diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index eab781195..28284b45d 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2534,6 +2534,85 @@ static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state)
 	}
 }
 
+static int gv11b_gr_update_sm_error_state(struct gk20a *g,
+		struct channel_gk20a *ch, u32 sm_id,
+		struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state)
+{
+	u32 gpc, tpc, sm, offset;
+	struct gr_gk20a *gr = &g->gr;
+	struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
+	int err = 0;
+
+	nvgpu_mutex_acquire(&g->dbg_sessions_lock);
+
+	gr->sm_error_states[sm_id].hww_global_esr =
+			sm_error_state->hww_global_esr;
+	gr->sm_error_states[sm_id].hww_warp_esr =
+			sm_error_state->hww_warp_esr;
+	gr->sm_error_states[sm_id].hww_warp_esr_pc =
+			sm_error_state->hww_warp_esr_pc;
+	gr->sm_error_states[sm_id].hww_global_esr_report_mask =
+			sm_error_state->hww_global_esr_report_mask;
+	gr->sm_error_states[sm_id].hww_warp_esr_report_mask =
+			sm_error_state->hww_warp_esr_report_mask;
+
+	err = gr_gk20a_disable_ctxsw(g);
+	if (err) {
+		nvgpu_err(g, "unable to stop gr ctxsw");
+		goto fail;
+	}
+
+	gpc = g->gr.sm_to_cluster[sm_id].gpc_index;
+	tpc = g->gr.sm_to_cluster[sm_id].tpc_index;
+	sm = g->gr.sm_to_cluster[sm_id].sm_index;
+
+	offset = gk20a_gr_gpc_offset(g, gpc) +
+			 gk20a_gr_tpc_offset(g, tpc) +
+			 gv11b_gr_sm_offset(g, sm);
+
+	if (gk20a_is_channel_ctx_resident(ch)) {
+		gk20a_writel(g,
+			gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset,
+			gr->sm_error_states[sm_id].hww_global_esr);
+		gk20a_writel(g,
+			gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset,
+			gr->sm_error_states[sm_id].hww_warp_esr);
+		gk20a_writel(g,
+			gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset,
+			gr->sm_error_states[sm_id].hww_warp_esr_pc);
+		gk20a_writel(g,
+			gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset,
+			gr->sm_error_states[sm_id].hww_global_esr_report_mask);
+		gk20a_writel(g,
+			gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset,
+			gr->sm_error_states[sm_id].hww_warp_esr_report_mask);
+	} else {
+		err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
+		if (err)
+			goto enable_ctxsw;
+
+		gr_gk20a_ctx_patch_write(g, ch_ctx,
+			gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() +
+			offset,
+			gr->sm_error_states[sm_id].hww_global_esr_report_mask,
+			true);
+		gr_gk20a_ctx_patch_write(g, ch_ctx,
+			gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() +
+			offset,
+			gr->sm_error_states[sm_id].hww_warp_esr_report_mask,
+			true);
+
+		gr_gk20a_ctx_patch_write_end(g, ch_ctx);
+	}
+
+enable_ctxsw:
+	err = gr_gk20a_enable_ctxsw(g);
+
+fail:
+	nvgpu_mutex_release(&g->dbg_sessions_lock);
+	return err;
+}
+
 void gv11b_init_gr(struct gpu_ops *gops)
 {
 	gp10b_init_gr(gops);
@@ -2598,4 +2677,5 @@ void gv11b_init_gr(struct gpu_ops *gops)
 	gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel;
 	gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend;
 	gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info;
+	gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state;
 }