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gpu: nvgpu: add doxygen for common MC unit

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Add doxygen details about Master Control (MC) common unit. Moved the
interrupt handling related variables to new structure nvgpu_mc.

JIRA NVGPU-2524

Change-Id: I61fb4ba325d9bd71e9505af01cd5a82e4e205833
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226019
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-10-25 01:15:26 +05:30
committed by Alex Waterman
parent b26acdeb87
commit f2b49f1c40
15 changed files with 272 additions and 98 deletions
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13
drivers/gpu/nvgpu/common/mc/mc.c
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@@ -48,18 +48,19 @@ static int cyclic_delta(int a, int b)
*/
void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
{
int stall_irq_threshold = nvgpu_atomic_read(&g->hw_irq_stall_count);
int nonstall_irq_threshold = nvgpu_atomic_read(&g->hw_irq_nonstall_count);
int stall_irq_threshold = nvgpu_atomic_read(&g->mc.hw_irq_stall_count);
int nonstall_irq_threshold =
nvgpu_atomic_read(&g->mc.hw_irq_nonstall_count);
/* wait until all stalling irqs are handled */
NVGPU_COND_WAIT(&g->sw_irq_stall_last_handled_cond,
NVGPU_COND_WAIT(&g->mc.sw_irq_stall_last_handled_cond,
cyclic_delta(stall_irq_threshold,
nvgpu_atomic_read(&g->sw_irq_stall_last_handled))
nvgpu_atomic_read(&g->mc.sw_irq_stall_last_handled))
<= 0, 0U);
/* wait until all non-stalling irqs are handled */
NVGPU_COND_WAIT(&g->sw_irq_nonstall_last_handled_cond,
NVGPU_COND_WAIT(&g->mc.sw_irq_nonstall_last_handled_cond,
cyclic_delta(nonstall_irq_threshold,
nvgpu_atomic_read(&g->sw_irq_nonstall_last_handled))
nvgpu_atomic_read(&g->mc.sw_irq_nonstall_last_handled))
<= 0, 0U);
}