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gpu: nvgpu: add doxygen for common MC unit

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Add doxygen details about Master Control (MC) common unit. Moved the
interrupt handling related variables to new structure nvgpu_mc.

JIRA NVGPU-2524

Change-Id: I61fb4ba325d9bd71e9505af01cd5a82e4e205833
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226019
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-10-25 01:15:26 +05:30
committed by Alex Waterman
parent b26acdeb87
commit f2b49f1c40
15 changed files with 272 additions and 98 deletions
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8
drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
View File

@@ -107,11 +107,11 @@ void gm20b_mc_disable(struct gk20a *g, u32 units)
nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x", units);
nvgpu_spinlock_acquire(&g->mc_enable_lock);
nvgpu_spinlock_acquire(&g->mc.enable_lock);
pmc = nvgpu_readl(g, mc_enable_r());
pmc &= ~units;
nvgpu_writel(g, mc_enable_r(), pmc);
nvgpu_spinlock_release(&g->mc_enable_lock);
nvgpu_spinlock_release(&g->mc.enable_lock);
}
void gm20b_mc_enable(struct gk20a *g, u32 units)
@@ -120,12 +120,12 @@ void gm20b_mc_enable(struct gk20a *g, u32 units)
nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x", units);
nvgpu_spinlock_acquire(&g->mc_enable_lock);
nvgpu_spinlock_acquire(&g->mc.enable_lock);
pmc = nvgpu_readl(g, mc_enable_r());
pmc |= units;
nvgpu_writel(g, mc_enable_r(), pmc);
pmc = nvgpu_readl(g, mc_enable_r());
nvgpu_spinlock_release(&g->mc_enable_lock);
nvgpu_spinlock_release(&g->mc.enable_lock);
nvgpu_udelay(MC_ENABLE_DELAY_US);
}

14
drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
View File

@@ -41,7 +41,7 @@ int mc_gp10b_intr_enable(struct gk20a *g)
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
@@ -49,15 +49,15 @@ int mc_gp10b_intr_enable(struct gk20a *g)
mc_intr_replayable_fault_pending_f() |
eng_intr_mask;
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f() |
eng_intr_mask;
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
return 0;
}
@@ -68,18 +68,18 @@ void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable)
if (enable) {
reg = mc_intr_en_set_r(NVGPU_MC_INTR_STALLING);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
mc_intr_pmu_pending_f();
nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
} else {
reg = mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
~mc_intr_pmu_pending_f();
nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
reg = mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING);
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] &=
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] &=
~mc_intr_pmu_pending_f();
nvgpu_writel(g, reg, mc_intr_pmu_pending_f());
}

4
drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
View File

@@ -148,7 +148,7 @@ void mc_gp10b_intr_stall_pause(struct gk20a *g)
void mc_gp10b_intr_stall_resume(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
}
u32 mc_gp10b_intr_nonstall(struct gk20a *g)
@@ -165,7 +165,7 @@ void mc_gp10b_intr_nonstall_pause(struct gk20a *g)
void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
bool mc_gp10b_is_intr1_pending(struct gk20a *g,

8
drivers/gpu/nvgpu/hal/mc/mc_gv100.c
View File

@@ -42,7 +42,7 @@ int mc_gv100_intr_enable(struct gk20a *g)
U32_MAX);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_hub_pending_f() |
mc_intr_priv_ring_pending_f() |
@@ -51,15 +51,15 @@ int mc_gv100_intr_enable(struct gk20a *g)
mc_intr_nvlink_pending_f() |
eng_intr_mask;
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f()
| eng_intr_mask;
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
return 0;
}

8
drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c
View File

@@ -42,7 +42,7 @@ int mc_gv11b_intr_enable(struct gk20a *g)
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_hub_pending_f() |
mc_intr_priv_ring_pending_f() |
@@ -50,15 +50,15 @@ int mc_gv11b_intr_enable(struct gk20a *g)
mc_intr_ltc_pending_f() |
eng_intr_mask;
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f()
| eng_intr_mask;
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
return 0;
}

4
drivers/gpu/nvgpu/hal/mc/mc_tu104.c
View File

@@ -142,7 +142,7 @@ static void intr_tu104_stall_enable(struct gk20a *g)
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
@@ -152,7 +152,7 @@ static void intr_tu104_stall_enable(struct gk20a *g)
eng_intr_mask;
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
}
static void intr_tu104_nonstall_enable(struct gk20a *g)