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gpu: nvgpu: add doxygen for common MC unit

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Add doxygen details about Master Control (MC) common unit. Moved the
interrupt handling related variables to new structure nvgpu_mc.

JIRA NVGPU-2524

Change-Id: I61fb4ba325d9bd71e9505af01cd5a82e4e205833
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226019
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-10-25 01:15:26 +05:30
committed by Alex Waterman
parent b26acdeb87
commit f2b49f1c40
15 changed files with 272 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -52,13 +52,13 @@ static void nvgpu_init_vars(struct gk20a *g)
struct device *dev = dev_from_gk20a(g);
struct gk20a_platform *platform = dev_get_drvdata(dev);
nvgpu_cond_init(&g->sw_irq_stall_last_handled_cond);
nvgpu_cond_init(&g->sw_irq_nonstall_last_handled_cond);
nvgpu_cond_init(&g->mc.sw_irq_stall_last_handled_cond);
nvgpu_cond_init(&g->mc.sw_irq_nonstall_last_handled_cond);
init_rwsem(&l->busy_lock);
nvgpu_rwsem_init(&g->deterministic_busy);
nvgpu_spinlock_init(&g->mc_enable_lock);
nvgpu_spinlock_init(&g->mc.enable_lock);
nvgpu_spinlock_init(&g->power_spinlock);

14
drivers/gpu/nvgpu/os/linux/intr.c
View File

@@ -47,7 +47,7 @@ irqreturn_t nvgpu_intr_stall(struct gk20a *g)
}
#endif
nvgpu_atomic_inc(&g->hw_irq_stall_count);
nvgpu_atomic_inc(&g->mc.hw_irq_stall_count);
#ifdef CONFIG_NVGPU_TRACE
trace_mc_gk20a_intr_stall_done(g->name);
@@ -66,13 +66,13 @@ irqreturn_t nvgpu_intr_thread_stall(struct gk20a *g)
trace_mc_gk20a_intr_thread_stall(g->name);
#endif
hw_irq_count = nvgpu_atomic_read(&g->hw_irq_stall_count);
hw_irq_count = nvgpu_atomic_read(&g->mc.hw_irq_stall_count);
g->ops.mc.isr_stall(g);
g->ops.mc.intr_stall_resume(g);
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
nvgpu_atomic_set(&g->mc.sw_irq_stall_last_handled, hw_irq_count);
nvgpu_cond_broadcast(&g->sw_irq_stall_last_handled_cond);
nvgpu_cond_broadcast(&g->mc.sw_irq_stall_last_handled_cond);
#ifdef CONFIG_NVGPU_TRACE
trace_mc_gk20a_intr_thread_stall_done(g->name);
@@ -114,14 +114,14 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g)
queue_work(l->nonstall_work_queue, &l->nonstall_fn_work);
}
hw_irq_count = nvgpu_atomic_inc_return(&g->hw_irq_nonstall_count);
hw_irq_count = nvgpu_atomic_inc_return(&g->mc.hw_irq_nonstall_count);
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->sw_irq_nonstall_last_handled, hw_irq_count);
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_last_handled, hw_irq_count);
g->ops.mc.intr_nonstall_resume(g);
nvgpu_cond_broadcast(&g->sw_irq_nonstall_last_handled_cond);
nvgpu_cond_broadcast(&g->mc.sw_irq_nonstall_last_handled_cond);
return IRQ_HANDLED;
}

48
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -543,11 +543,11 @@ static int gk20a_lockout_registers(struct gk20a *g)
int nvgpu_enable_irqs(struct gk20a *g)
{
if (!g->irqs_enabled) {
enable_irq(g->irq_stall);
if (g->irq_stall != g->irq_nonstall)
enable_irq(g->irq_nonstall);
g->irqs_enabled = true;
if (!g->mc.irqs_enabled) {
enable_irq(g->mc.irq_stall);
if (g->mc.irq_stall != g->mc.irq_nonstall)
enable_irq(g->mc.irq_nonstall);
g->mc.irqs_enabled = true;
}
return 0;
@@ -555,11 +555,11 @@ int nvgpu_enable_irqs(struct gk20a *g)
void nvgpu_disable_irqs(struct gk20a *g)
{
if (g->irqs_enabled) {
disable_irq(g->irq_stall);
if (g->irq_stall != g->irq_nonstall)
disable_irq(g->irq_nonstall);
g->irqs_enabled = false;
if (g->mc.irqs_enabled) {
disable_irq(g->mc.irq_stall);
if (g->mc.irq_stall != g->mc.irq_nonstall)
disable_irq(g->mc.irq_nonstall);
g->mc.irqs_enabled = false;
}
}
@@ -642,7 +642,7 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
goto done;
/* disable IRQs and wait for completion */
irqs_enabled = g->irqs_enabled;
irqs_enabled = g->mc.irqs_enabled;
nvgpu_disable_irqs(g);
gk20a_scale_suspend(dev);
@@ -1156,9 +1156,9 @@ void nvgpu_free_irq(struct gk20a *g)
{
struct device *dev = dev_from_gk20a(g);
devm_free_irq(dev, g->irq_stall, g);
if (g->irq_stall != g->irq_nonstall)
devm_free_irq(dev, g->irq_nonstall, g);
devm_free_irq(dev, g->mc.irq_stall, g);
if (g->mc.irq_stall != g->mc.irq_nonstall)
devm_free_irq(dev, g->mc.irq_nonstall, g);
}
/*
@@ -1572,37 +1572,37 @@ static int gk20a_probe(struct platform_device *dev)
if (nvgpu_platform_is_simulation(gk20a))
nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
gk20a->irq_stall = platform_get_irq(dev, 0);
gk20a->irq_nonstall = platform_get_irq(dev, 1);
if ((int)gk20a->irq_stall < 0 || (int)gk20a->irq_nonstall < 0) {
gk20a->mc.irq_stall = platform_get_irq(dev, 0);
gk20a->mc.irq_nonstall = platform_get_irq(dev, 1);
if ((int)gk20a->mc.irq_stall < 0 || (int)gk20a->mc.irq_nonstall < 0) {
err = -ENXIO;
goto return_err;
}
err = devm_request_threaded_irq(&dev->dev,
gk20a->irq_stall,
gk20a->mc.irq_stall,
gk20a_intr_isr_stall,
gk20a_intr_thread_stall,
0, "gk20a_stall", gk20a);
if (err) {
dev_err(&dev->dev,
"failed to request stall intr irq @ %d\n",
gk20a->irq_stall);
gk20a->mc.irq_stall);
goto return_err;
}
err = devm_request_irq(&dev->dev,
gk20a->irq_nonstall,
gk20a->mc.irq_nonstall,
gk20a_intr_isr_nonstall,
0, "gk20a_nonstall", gk20a);
if (err) {
dev_err(&dev->dev,
"failed to request non-stall intr irq @ %d\n",
gk20a->irq_nonstall);
gk20a->mc.irq_nonstall);
goto return_err;
}
disable_irq(gk20a->irq_stall);
if (gk20a->irq_stall != gk20a->irq_nonstall)
disable_irq(gk20a->irq_nonstall);
disable_irq(gk20a->mc.irq_stall);
if (gk20a->mc.irq_stall != gk20a->mc.irq_nonstall)
disable_irq(gk20a->mc.irq_nonstall);
err = gk20a_init_support(dev);
if (err)

14
drivers/gpu/nvgpu/os/linux/pci.c
View File

@@ -484,15 +484,15 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
g->msi_enabled = true;
#endif
g->irq_stall = pdev->irq;
g->irq_nonstall = pdev->irq;
if ((int)g->irq_stall < 0) {
g->mc.irq_stall = pdev->irq;
g->mc.irq_nonstall = pdev->irq;
if ((int)g->mc.irq_stall < 0) {
err = -ENXIO;
goto err_disable_msi;
}
err = devm_request_threaded_irq(&pdev->dev,
g->irq_stall,
g->mc.irq_stall,
nvgpu_pci_isr,
nvgpu_pci_intr_thread,
#if defined(CONFIG_PCI_MSI)
@@ -501,10 +501,10 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
IRQF_SHARED, "nvgpu", g);
if (err) {
nvgpu_err(g,
"failed to request irq @ %d", g->irq_stall);
"failed to request irq @ %d", g->mc.irq_stall);
goto err_disable_msi;
}
disable_irq(g->irq_stall);
disable_irq(g->mc.irq_stall);
err = nvgpu_pci_init_support(pdev);
if (err)
@@ -629,7 +629,7 @@ static void nvgpu_pci_remove(struct pci_dev *pdev)
/* IRQ does not need to be enabled in MSI as the line is not
* shared
*/
enable_irq(g->irq_stall);
enable_irq(g->mc.irq_stall);
}
#endif
nvgpu_pci_pm_deinit(&pdev->dev);

2
drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
View File

@@ -385,7 +385,7 @@ int vgpu_probe(struct platform_device *pdev)
init_rwsem(&l->busy_lock);
nvgpu_spinlock_init(&gk20a->mc_enable_lock);
nvgpu_spinlock_init(&gk20a->mc.enable_lock);
gk20a->ch_wdt_init_limit_ms = platform->ch_wdt_init_limit_ms;