From f31171a66705219c8eaa714eb3f731fa1ab87a1b Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Tue, 26 Nov 2019 17:50:53 -0800 Subject: [PATCH] gpu: nvgpu: unit: mm: flush_gv11b_fusa unit test This unit test covers most of the nvgpu.hal.mm.cache.flush_gv11b_fusa module lines and almost all branches. Jira NVGPU-2218 Change-Id: I565cf289079f754d3f76b6680e853d1859c52283 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/2248383 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- Makefile.umbrella.tmk | 1 + userspace/Makefile.sources | 1 + userspace/SWUTS.h | 1 + userspace/SWUTS.sources | 1 + userspace/required_tests.json | 48 +++ .../mm/hal/cache/flush_gv11b_fusa/Makefile | 26 ++ .../flush_gv11b_fusa/Makefile.interface.tmk | 35 ++ .../hal/cache/flush_gv11b_fusa/Makefile.tmk | 35 ++ .../cache/flush_gv11b_fusa/flush-gv11b-fusa.c | 308 ++++++++++++++++++ .../cache/flush_gv11b_fusa/flush-gv11b-fusa.h | 102 ++++++ 10 files changed, 558 insertions(+) create mode 100644 userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile create mode 100644 userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.interface.tmk create mode 100644 userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.tmk create mode 100644 userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c create mode 100644 userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.h diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index 78b905680..d53d8a1ad 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -66,6 +66,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/mm/dma NV_REPOSITORY_COMPONENTS += userspace/units/mm/gmmu/pd_cache NV_REPOSITORY_COMPONENTS += userspace/units/mm/gmmu/page_table NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/cache/flush_gk20a_fusa +NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/cache/flush_gv11b_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gp10b_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gv11b_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/mm diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index c499b1c98..3079658e2 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -73,6 +73,7 @@ UNITS := \ $(UNIT_SRC)/mm/gmmu/pd_cache \ $(UNIT_SRC)/mm/gmmu/page_table \ $(UNIT_SRC)/mm/hal/cache/flush_gk20a_fusa \ + $(UNIT_SRC)/mm/hal/cache/flush_gv11b_fusa \ $(UNIT_SRC)/mm/hal/gp10b_fusa \ $(UNIT_SRC)/mm/hal/gv11b_fusa \ $(UNIT_SRC)/mm/mm \ diff --git a/userspace/SWUTS.h b/userspace/SWUTS.h index e6581c0c8..e9f4b525b 100644 --- a/userspace/SWUTS.h +++ b/userspace/SWUTS.h @@ -69,6 +69,7 @@ * - @ref SWUTS-mm-dma * - @ref SWUTS-mm-gmmu-page_table * - @ref SWUTS-mm-hal-cache-flush-gk20a-fusa + * - @ref SWUTS-mm-hal-cache-flush-gv11b-fusa * - @ref SWUTS-mm-hal-gp10b_fusa * - @ref SWUTS-mm-hal-gv11b-fusa * - @ref SWUTS-mm-nvgpu-mem diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index c5992fb56..73097ef5b 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -45,6 +45,7 @@ INPUT += ../../../userspace/units/mm/as/as.h INPUT += ../../../userspace/units/mm/dma/dma.h INPUT += ../../../userspace/units/mm/gmmu/page_table/page_table.h INPUT += ../../../userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h +INPUT += ../../../userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gv11b-fusa.h INPUT += ../../../userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.h INPUT += ../../../userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.h INPUT += ../../../userspace/units/mm/nvgpu_mem/nvgpu_mem.h diff --git a/userspace/required_tests.json b/userspace/required_tests.json index 63bd2a0c5..8c2c5a168 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -821,6 +821,54 @@ "unit": "flush_gk20a_fusa", "test_level": 0 }, + { + "test": "test_env_clean", + "case": "env_clean", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_env_init", + "case": "env_init", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_mm_l2_flush", + "case": "mm_l2_flush_s0", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_mm_l2_flush", + "case": "mm_l2_flush_s1", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_mm_l2_flush", + "case": "mm_l2_flush_s2", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_mm_l2_flush", + "case": "mm_l2_flush_s3", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_mm_l2_flush", + "case": "mm_l2_flush_s4", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_mm_l2_flush", + "case": "mm_l2_flush_s5", + "unit": "flush_gv11b_fusa", + "test_level": 0 + }, { "test": "test_fuse_gm20b_basic_fuses", "case": "fuse_gm20b_basic_fuses", diff --git a/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile b/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile new file mode 100644 index 000000000..2f6502e38 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = flush-gv11b-fusa.o +MODULE = flush-gv11b-fusa + +include ../../../../Makefile.units diff --git a/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.interface.tmk b/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.interface.tmk new file mode 100644 index 000000000..0885af778 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=flush-gv11b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.tmk b/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.tmk new file mode 100644 index 000000000..04af10452 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=flush-gv11b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c b/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c new file mode 100644 index 000000000..7140e2ca2 --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "os/posix/os_posix.h" + +#include "hal/fb/fb_gv11b.h" +#include "hal/fb/intr/fb_intr_gv11b.h" +#include "hal/fifo/ramin_gk20a.h" +#include "hal/fifo/ramin_gp10b.h" +#include "hal/mm/cache/flush_gk20a.h" +#include "hal/mm/gmmu/gmmu_gp10b.h" +#include "hal/mm/mm_gp10b.h" +#include "hal/mm/mm_gv11b.h" +#include "hal/mm/mmu_fault/mmu_fault_gv11b.h" + +#include "hal/mm/cache/flush_gv11b.h" + +#include + +#include +#include + +#include "flush-gv11b-fusa.h" + +/* + * Write callback (for all nvgpu_writel calls). + */ +#define WR_FLUSH_0 0 +#define WR_FLUSH_1 1 + +static u32 write_specific_value; + +static void writel_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + if (access->addr == flush_l2_flush_dirty_r()) { + nvgpu_posix_io_writel_reg_space(g, access->addr, + write_specific_value); + } else { + nvgpu_posix_io_writel_reg_space(g, access->addr, access->value); + } +} + +/* + * Read callback, similar to the write callback above. + */ +static void readl_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + access->value = nvgpu_posix_io_readl_reg_space(g, access->addr); +} + +/* + * Define all the callbacks to be used during the test. Typically all + * write operations use the same callback, likewise for all read operations. + */ +static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = { + /* Write APIs all can use the same accessor. */ + .writel = writel_access_reg_fn, + .writel_check = writel_access_reg_fn, + .bar1_writel = writel_access_reg_fn, + .usermode_writel = writel_access_reg_fn, + + /* Likewise for the read APIs. */ + .__readl = readl_access_reg_fn, + .readl = readl_access_reg_fn, + .bar1_readl = readl_access_reg_fn, +}; + +static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU) +{ + if (is_iGPU) { + nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true); + } else { + nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false); + } +} + +static int init_mm(struct unit_module *m, struct gk20a *g) +{ + u64 low_hole, aperture_size; + struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g); + struct mm_gk20a *mm = &g->mm; + + p->mm_is_iommuable = true; + + /* Minimum HALs for page_table */ + g->ops.mm.gmmu.get_default_big_page_size = + gp10b_mm_get_default_big_page_size; + g->ops.mm.init_inst_block = gv11b_mm_init_inst_block; + g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels; + g->ops.ramin.init_pdb = gp10b_ramin_init_pdb; + g->ops.ramin.alloc_size = gk20a_ramin_alloc_size; + g->ops.mm.setup_hw = nvgpu_mm_setup_hw; + g->ops.fb.init_hw = gv11b_fb_init_hw; + g->ops.fb.intr.enable = gv11b_fb_intr_enable; + g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush; + g->ops.mm.mmu_fault.info_mem_destroy = + gv11b_mm_mmu_fault_info_mem_destroy; + + nvgpu_posix_register_io(g, &mmu_faults_callbacks); + nvgpu_posix_io_init_reg_space(g); + + /* Register space: FB_MMU */ + if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x800) != 0) { + unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n"); + } + + /* + * Initialize VM space for system memory to be used throughout this + * unit module. + * Values below are similar to those used in nvgpu_init_system_vm() + */ + low_hole = SZ_4K * 16UL; + aperture_size = GK20A_PMU_VA_SIZE; + mm->pmu.aperture_size = GK20A_PMU_VA_SIZE; + + mm->pmu.vm = nvgpu_vm_init(g, + g->ops.mm.gmmu.get_default_big_page_size(), + low_hole, + aperture_size - low_hole, + aperture_size, + true, + false, + false, + "system"); + if (mm->pmu.vm == NULL) { + unit_return_fail(m, "'system' nvgpu_vm_init failed\n"); + } + + /* BAR1 memory space */ + mm->bar1.aperture_size = U32(16) << 20U; + mm->bar1.vm = nvgpu_vm_init(g, + g->ops.mm.gmmu.get_default_big_page_size(), + SZ_4K, mm->bar1.aperture_size - SZ_4K, + mm->bar1.aperture_size, false, false, false, "bar1"); + if (mm->bar1.vm == NULL) { + unit_return_fail(m, "'bar1' nvgpu_vm_init failed\n"); + } + + /* + * This initialization will make sure that correct aperture mask + * is returned */ + g->mm.mmu_wr_mem.aperture = APERTURE_SYSMEM; + g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM; + + return UNIT_SUCCESS; +} + +int test_env_init(struct unit_module *m, struct gk20a *g, void *args) +{ + g->log_mask = 0; + + init_platform(m, g, true); + + if (init_mm(m, g) != 0) { + unit_return_fail(m, "nvgpu_init_mm_support failed\n"); + } + + write_specific_value = 0; + + return UNIT_SUCCESS; +} + +#define F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL 0 +#define F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL 1 +#define F_GV11B_L2_FLUSH_FB_FLUSH_FAIL 2 +#define F_GV11B_L2_FLUSH_L2_FLUSH_FAIL 3 +#define F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL 4 +#define F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL 5 + +const char *m_gv11b_mm_l2_flush_str[] = { + "pass_bar1_bind_not_null", + "pass_bar1_bind_null", + "fb_flush_fail", + "l2_flush_fail", + "tlb_invalidate_fail", + "fb_flush_2_fail", +}; + +static u32 stub_fb_flush_fail; +static bool stub_tlb_invalidate_fail; + +static int stub_mm_fb_flush(struct gk20a *g) +{ + if (stub_fb_flush_fail == 0) { + return -EBUSY; + } + + stub_fb_flush_fail--; + return 0; +} + +static int stub_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) +{ + return 0; +} + +static int stub_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) +{ + if (stub_tlb_invalidate_fail) { + return -ETIMEDOUT; + } + + return 0; +} + +int test_gv11b_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args) +{ + struct gpu_ops gops = g->ops; + int err; + int ret = UNIT_FAIL; + u64 branch = (u64)args; + + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON); + g->ops.mm.cache.fb_flush = stub_mm_fb_flush; + g->ops.fb.tlb_invalidate = stub_fb_tlb_invalidate; + + stub_fb_flush_fail = (branch == F_GV11B_L2_FLUSH_FB_FLUSH_FAIL) ? + 0U : (branch == F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL ? 1U : 2U); + + /* Write data to flush dirty addr will control l2_flush() output */ + write_specific_value = branch == F_GV11B_L2_FLUSH_L2_FLUSH_FAIL ? + WR_FLUSH_1 : WR_FLUSH_0; + + g->ops.bus.bar1_bind = + ((branch == F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL) || + (branch == F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL)) ? + NULL : stub_bus_bar1_bind; + + stub_tlb_invalidate_fail = + branch == F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL ? true : false; + + err = gv11b_mm_l2_flush(g, false); + + unit_info(m, "%p\n", g->mm.bar1.vm->pdb.mem); + + if ((branch == F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL) || + (branch == F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL)) { + unit_assert(err == 0, goto done); + } else { + unit_assert(err != 0, goto done); + } + + ret = UNIT_SUCCESS; +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: failed at %s\n", __func__, + m_gv11b_mm_l2_flush_str[branch]); + } + nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF); + g->ops = gops; + return ret; +} + +int test_env_clean(struct unit_module *m, struct gk20a *g, void *args) +{ + g->log_mask = 0; + + nvgpu_vm_put(g->mm.pmu.vm); + nvgpu_vm_put(g->mm.bar1.vm); + + return UNIT_SUCCESS; +} + +struct unit_module_test mm_flush_gv11b_fusa_tests[] = { + UNIT_TEST(env_init, test_env_init, (void *)0, 0), + UNIT_TEST(mm_l2_flush_s0, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL, 0), + UNIT_TEST(mm_l2_flush_s1, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL, 0), + UNIT_TEST(mm_l2_flush_s2, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_FB_FLUSH_FAIL, 0), + UNIT_TEST(mm_l2_flush_s3, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_L2_FLUSH_FAIL, 0), + UNIT_TEST(mm_l2_flush_s4, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL, 0), + UNIT_TEST(mm_l2_flush_s5, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL, 0), + UNIT_TEST(env_clean, test_env_clean, NULL, 0), +}; + +UNIT_MODULE(flush_gv11b_fusa, mm_flush_gv11b_fusa_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.h b/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.h new file mode 100644 index 000000000..abe41ed2e --- /dev/null +++ b/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_MM_HAL_CACHE_FLUSH_GV11B_FUSA_H +#define UNIT_MM_HAL_CACHE_FLUSH_GV11B_FUSA_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-mm-hal-cache-flush-gv11b-fusa + * @{ + * + * Software Unit Test Specification for mm.hal.cache.flush_gv11b_fusa + */ + +/** + * Test specification for: test_env_init + * + * Description: Initialize environment for MM tests + * + * Test Type: Feature based + * + * Targets: None + * + * Input: None + * + * Steps: + * - Init HALs and initialize VMs similar to nvgpu_init_system_vm(). + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_env_init(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_mm_l2_flush + * + * Description: Test L2 flush + * + * Test Type: Feature based + * + * Targets: gv11b_mm_l2_flush + * + * Input: test_env_init, args (value can be + * F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL, + * F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL, F_GV11B_L2_FLUSH_FB_FLUSH_FAIL, + * F_GV11B_L2_FLUSH_L2_FLUSH_FAIL, F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL, + * F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL) + * + * Steps: + * - Invoke L2 flush command + * - Test L2 flush with various scenarios as below: + * - fb_flush is successful or fails + * - l2_flush passes or fails + * - bar1_bind is populated or not populated + * - tlb_invalidate passes or fails + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gv11b_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_env_clean + * + * Description: Cleanup test environment + * + * Test Type: Feature based + * + * Targets: None + * + * Input: test_env_init + * + * Steps: + * - Destroy memory and VMs initialized for the test. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_env_clean(struct unit_module *m, struct gk20a *g, void *args); + +/** @} */ +#endif /* UNIT_MM_HAL_CACHE_FLUSH_GV11B_FUSA_H */