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Open source GPL/LGPL release
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278
drivers/gpu/nvgpu/common/fifo/watchdog.c
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278
drivers/gpu/nvgpu/common/fifo/watchdog.c
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/*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/watchdog.h>
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#include <nvgpu/error_notifier.h>
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#include <nvgpu/watchdog.h>
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#include <nvgpu/string.h>
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struct nvgpu_channel_wdt {
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struct gk20a *g;
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/* lock protects the running timer state */
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struct nvgpu_spinlock lock;
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struct nvgpu_timeout timer;
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bool running;
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struct nvgpu_channel_wdt_state ch_state;
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/* lock not needed */
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u32 limit_ms;
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bool enabled;
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};
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struct nvgpu_channel_wdt *nvgpu_channel_wdt_alloc(struct gk20a *g)
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{
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struct nvgpu_channel_wdt *wdt = nvgpu_kzalloc(g, sizeof(*wdt));
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if (wdt == NULL) {
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return NULL;
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}
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wdt->g = g;
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nvgpu_spinlock_init(&wdt->lock);
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wdt->enabled = true;
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wdt->limit_ms = g->ch_wdt_init_limit_ms;
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return wdt;
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}
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void nvgpu_channel_wdt_destroy(struct nvgpu_channel_wdt *wdt)
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{
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nvgpu_kfree(wdt->g, wdt);
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}
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void nvgpu_channel_wdt_enable(struct nvgpu_channel_wdt *wdt)
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{
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wdt->enabled = true;
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}
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void nvgpu_channel_wdt_disable(struct nvgpu_channel_wdt *wdt)
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{
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wdt->enabled = false;
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}
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bool nvgpu_channel_wdt_enabled(struct nvgpu_channel_wdt *wdt)
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{
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return wdt->enabled;
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}
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void nvgpu_channel_wdt_set_limit(struct nvgpu_channel_wdt *wdt, u32 limit_ms)
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{
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wdt->limit_ms = limit_ms;
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}
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u32 nvgpu_channel_wdt_limit(struct nvgpu_channel_wdt *wdt)
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{
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return wdt->limit_ms;
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}
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static void nvgpu_channel_wdt_init(struct nvgpu_channel_wdt *wdt,
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struct nvgpu_channel_wdt_state *state)
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{
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struct gk20a *g = wdt->g;
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int ret;
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ret = nvgpu_timeout_init(g, &wdt->timer,
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wdt->limit_ms,
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NVGPU_TIMER_CPU_TIMER);
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if (ret != 0) {
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nvgpu_err(g, "timeout_init failed: %d", ret);
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return;
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}
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wdt->ch_state = *state;
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wdt->running = true;
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}
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/**
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* Start a timeout counter (watchdog) on this channel.
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*
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* Trigger a watchdog to recover the channel after the per-platform timeout
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* duration (but strictly no earlier) if the channel hasn't advanced within
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* that time.
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*
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* If the timeout is already running, do nothing. This should be called when
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* new jobs are submitted. The timeout will stop when the last tracked job
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* finishes, making the channel idle.
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*/
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void nvgpu_channel_wdt_start(struct nvgpu_channel_wdt *wdt,
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struct nvgpu_channel_wdt_state *state)
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{
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if (!nvgpu_is_timeouts_enabled(wdt->g)) {
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return;
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}
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if (!wdt->enabled) {
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return;
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}
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nvgpu_spinlock_acquire(&wdt->lock);
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if (wdt->running) {
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nvgpu_spinlock_release(&wdt->lock);
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return;
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}
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nvgpu_channel_wdt_init(wdt, state);
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nvgpu_spinlock_release(&wdt->lock);
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}
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/**
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* Stop a running timeout counter (watchdog) on this channel.
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*
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* Make the watchdog consider the channel not running, so that it won't get
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* recovered even if no progress is detected. Progress is not tracked if the
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* watchdog is turned off.
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*
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* No guarantees are made about concurrent execution of the timeout handler.
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* (This should be called from an update handler running in the same thread
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* with the watchdog.)
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*/
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bool nvgpu_channel_wdt_stop(struct nvgpu_channel_wdt *wdt)
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{
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bool was_running;
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nvgpu_spinlock_acquire(&wdt->lock);
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was_running = wdt->running;
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wdt->running = false;
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nvgpu_spinlock_release(&wdt->lock);
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return was_running;
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}
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/**
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* Continue a previously stopped timeout
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*
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* Enable the timeout again but don't reinitialize its timer.
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*
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* No guarantees are made about concurrent execution of the timeout handler.
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* (This should be called from an update handler running in the same thread
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* with the watchdog.)
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*/
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void nvgpu_channel_wdt_continue(struct nvgpu_channel_wdt *wdt)
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{
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nvgpu_spinlock_acquire(&wdt->lock);
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wdt->running = true;
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nvgpu_spinlock_release(&wdt->lock);
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}
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/**
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* Reset the counter of a timeout that is in effect.
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*
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* If this channel has an active timeout, act as if something happened on the
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* channel right now.
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*
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* Rewinding a stopped counter is irrelevant; this is a no-op for non-running
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* timeouts. Stopped timeouts can only be started (which is technically a
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* rewind too) or continued (where the stop is actually pause).
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*/
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void nvgpu_channel_wdt_rewind(struct nvgpu_channel_wdt *wdt,
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struct nvgpu_channel_wdt_state *state)
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{
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nvgpu_spinlock_acquire(&wdt->lock);
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if (wdt->running) {
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nvgpu_channel_wdt_init(wdt, state);
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}
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nvgpu_spinlock_release(&wdt->lock);
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}
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/**
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* Check if the watchdog is running.
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*
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* A running watchdog means one that is requested to run and expire in the
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* future. The state of a running watchdog has to be checked periodically to
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* see if it's expired.
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*/
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bool nvgpu_channel_wdt_running(struct nvgpu_channel_wdt *wdt)
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{
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bool running;
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nvgpu_spinlock_acquire(&wdt->lock);
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running = wdt->running;
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nvgpu_spinlock_release(&wdt->lock);
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return running;
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}
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/**
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* Check if a channel has been stuck for the watchdog limit.
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*
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* Test if this channel has really got stuck at this point by checking if its
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* {gp,pb}_get have advanced or not. If progress was detected, start the timer
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* from zero again. If no {gp,pb}_get action happened in the watchdog time
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* limit, return true. Else return false.
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*/
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static bool nvgpu_channel_wdt_handler(struct nvgpu_channel_wdt *wdt,
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struct nvgpu_channel_wdt_state *state)
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{
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struct gk20a *g = wdt->g;
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struct nvgpu_channel_wdt_state previous_state;
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nvgpu_log_fn(g, " ");
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/* Get status but keep timer running */
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nvgpu_spinlock_acquire(&wdt->lock);
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previous_state = wdt->ch_state;
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nvgpu_spinlock_release(&wdt->lock);
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if (nvgpu_memcmp((const u8 *)state,
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(const u8 *)&previous_state,
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sizeof(*state)) != 0) {
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/* Channel has advanced, timer keeps going but resets */
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nvgpu_channel_wdt_rewind(wdt, state);
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return false;
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}
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if (!nvgpu_timeout_peek_expired(&wdt->timer)) {
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/* Seems stuck but waiting to time out */
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return false;
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}
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return true;
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}
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/**
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* Test if the per-channel watchdog is on; check the timeout in that case.
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*
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* Each channel has an expiration time based watchdog. The timer is
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* (re)initialized in two situations: when a new job is submitted on an idle
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* channel and when the timeout is checked but progress is detected. The
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* watchdog timeout limit is a coarse sliding window.
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*
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* The timeout is stopped (disabled) after the last job in a row finishes
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* and marks the channel idle.
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*/
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bool nvgpu_channel_wdt_check(struct nvgpu_channel_wdt *wdt,
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struct nvgpu_channel_wdt_state *state)
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{
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bool running;
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nvgpu_spinlock_acquire(&wdt->lock);
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running = wdt->running;
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nvgpu_spinlock_release(&wdt->lock);
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if (running) {
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return nvgpu_channel_wdt_handler(wdt, state);
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} else {
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return false;
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}
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}
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