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git://nv-tegra.nvidia.com/linux-nvgpu.git
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Open source GPL/LGPL release
This commit is contained in:
svcmobrel-release
333
drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
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333
drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
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/*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/pmu/clk/clk.h>
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#include <nvgpu/pmu/perf.h>
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#include <nvgpu/pmu/cmd.h>
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#include <nvgpu/pmu/super_surface.h>
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#include <nvgpu/pmu/pmu_pstate.h>
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#include <nvgpu/pmu/perf.h>
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#include <common/pmu/boardobj/boardobj.h>
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#include "change_seq.h"
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#include "perf.h"
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static int perf_change_seq_sw_setup_super(struct gk20a *g,
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struct change_seq *p_change_seq)
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{
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int status = 0;
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nvgpu_log_fn(g, " ");
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/* Initialize parameters */
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p_change_seq->client_lock_mask = 0;
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p_change_seq->version = CTRL_PERF_CHANGE_SEQ_VERSION_35;
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status = nvgpu_boardobjgrpmask_init(
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&p_change_seq->clk_domains_exclusion_mask.super,
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32U, ((void*)0));
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if (status != 0) {
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nvgpu_err(g, "clk_domains_exclusion_mask failed to init %d",
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status);
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goto perf_change_seq_sw_setup_super_exit;
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}
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status = nvgpu_boardobjgrpmask_init(
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&p_change_seq->clk_domains_inclusion_mask.super,
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32U, ((void*)0));
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if (status != 0) {
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nvgpu_err(g, "clk_domains_inclusion_mask failed to init %d",
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status);
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goto perf_change_seq_sw_setup_super_exit;
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}
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perf_change_seq_sw_setup_super_exit:
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return status;
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}
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int perf_change_seq_sw_setup(struct gk20a *g)
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{
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struct change_seq_pmu *perf_change_seq_pmu =
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&(g->pmu->perf_pmu->changeseq_pmu);
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int status = 0;
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nvgpu_log_fn(g, " ");
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(void) memset(perf_change_seq_pmu, 0,
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sizeof(struct change_seq_pmu));
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status = perf_change_seq_sw_setup_super(g, &perf_change_seq_pmu->super);
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if (status != 0) {
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goto exit;
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}
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perf_change_seq_pmu->super.b_enabled_pmu_support = true;
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/*exclude MCLK, may not be needed as MCLK is already fixed */
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perf_change_seq_pmu->super.clk_domains_exclusion_mask.super.data[0]
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= 0x04U;
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perf_change_seq_pmu->b_vf_point_check_ignore = false;
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perf_change_seq_pmu->b_lock = false;
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perf_change_seq_pmu->cpu_step_id_mask = 0;
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perf_change_seq_pmu->cpu_adverised_step_id_mask = 0;
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perf_change_seq_pmu->change_state = 0U;
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exit:
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return status;
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}
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static void build_change_seq_boot (struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = g->pmu;
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struct change_seq_pmu *perf_change_seq_pmu =
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&(g->pmu->perf_pmu->changeseq_pmu);
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struct change_seq_pmu_script *script_last =
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&perf_change_seq_pmu->script_last;
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u8 num_domains = 0U;
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nvgpu_log_fn(g, " ");
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script_last->super_surface_offset =
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nvgpu_pmu_get_ss_member_set_offset(g, pmu,
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NV_PMU_SUPER_SURFACE_MEMBER_CHANGE_SEQ_GRP) +
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(u32)(sizeof(struct perf_change_seq_pmu_script) *
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SEQ_SCRIPT_LAST);
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nvgpu_mem_rd_n(g, nvgpu_pmu_super_surface_mem(g,
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pmu, pmu->super_surface),
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script_last->super_surface_offset,
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&script_last->buf,
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(u32) sizeof(struct perf_change_seq_pmu_script));
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script_last->buf.change.data.flags = CTRL_PERF_CHANGE_SEQ_CHANGE_NONE;
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num_domains = nvgpu_pmu_clk_domain_update_clk_info(g,
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&script_last->buf.change.data.clk_list);
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script_last->buf.change.data.clk_list.num_domains = num_domains;
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nvgpu_pmu_dbg(g,"Total domains = %d\n",
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script_last->buf.change.data.clk_list.num_domains);
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/* Assume everything is P0 - Need to find the index for P0 */
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script_last->buf.change.data.pstate_index =
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perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);
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nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g,
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pmu, pmu->super_surface),
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script_last->super_surface_offset,
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&script_last->buf,
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(u32) sizeof(struct perf_change_seq_pmu_script));
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return;
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}
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int perf_change_seq_pmu_setup(struct gk20a *g)
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{
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struct nv_pmu_rpc_perf_change_seq_info_get info_get;
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struct nv_pmu_rpc_perf_change_seq_info_set info_set;
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struct nvgpu_pmu *pmu = g->pmu;
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struct change_seq_pmu *perf_change_seq_pmu =
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&(g->pmu->perf_pmu->changeseq_pmu);
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int status;
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/* Do this till we enable performance table */
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build_change_seq_boot(g);
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(void) memset(&info_get, 0,
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sizeof(struct nv_pmu_rpc_perf_change_seq_info_get));
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(void) memset(&info_set, 0,
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sizeof(struct nv_pmu_rpc_perf_change_seq_info_set));
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PMU_RPC_EXECUTE_CPB(status, pmu, PERF, CHANGE_SEQ_INFO_GET, &info_get, 0);
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if (status != 0) {
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nvgpu_err(g,
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"Failed to execute Change Seq GET RPC status=0x%x",
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status);
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goto perf_change_seq_pmu_setup_exit;
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}
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info_set.info_set.super.version = perf_change_seq_pmu->super.version;
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status = nvgpu_boardobjgrpmask_export(
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&perf_change_seq_pmu->super.clk_domains_exclusion_mask.super,
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perf_change_seq_pmu->
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super.clk_domains_exclusion_mask.super.bitcount,
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&info_set.info_set.super.clk_domains_exclusion_mask.super);
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if ( status != 0 ) {
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nvgpu_err(g, "Could not export clkdomains exclusion mask");
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goto perf_change_seq_pmu_setup_exit;
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}
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status = nvgpu_boardobjgrpmask_export(
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&perf_change_seq_pmu->super.clk_domains_inclusion_mask.super,
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perf_change_seq_pmu->
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super.clk_domains_inclusion_mask.super.bitcount,
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&info_set.info_set.super.clk_domains_inclusion_mask.super);
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if ( status != 0 ) {
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nvgpu_err(g, "Could not export clkdomains inclusion mask");
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goto perf_change_seq_pmu_setup_exit;
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}
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info_set.info_set.b_vf_point_check_ignore =
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perf_change_seq_pmu->b_vf_point_check_ignore;
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info_set.info_set.cpu_step_id_mask =
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perf_change_seq_pmu->cpu_step_id_mask;
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info_set.info_set.b_lock =
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perf_change_seq_pmu->b_lock;
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perf_change_seq_pmu->script_last.super_surface_offset =
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nvgpu_pmu_get_ss_member_set_offset(g, pmu,
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NV_PMU_SUPER_SURFACE_MEMBER_CHANGE_SEQ_GRP) +
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(u32)(sizeof(struct perf_change_seq_pmu_script) *
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SEQ_SCRIPT_LAST);
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nvgpu_mem_rd_n(g, nvgpu_pmu_super_surface_mem(g,
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pmu, pmu->super_surface),
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perf_change_seq_pmu->script_last.super_surface_offset,
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&perf_change_seq_pmu->script_last.buf,
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(u32) sizeof(struct perf_change_seq_pmu_script));
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/* Assume everything is P0 - Need to find the index for P0 */
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perf_change_seq_pmu->script_last.buf.change.data.pstate_index =
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perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);;
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nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g,
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pmu, pmu->super_surface),
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perf_change_seq_pmu->script_last.super_surface_offset,
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&perf_change_seq_pmu->script_last.buf,
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(u32) sizeof(struct perf_change_seq_pmu_script));
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/* Continue with PMU setup, assume FB map is done */
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PMU_RPC_EXECUTE_CPB(status, pmu, PERF, CHANGE_SEQ_INFO_SET, &info_set, 0);
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if (status != 0) {
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nvgpu_err(g,
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"Failed to execute Change Seq SET RPC status=0x%x",
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status);
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goto perf_change_seq_pmu_setup_exit;
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}
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perf_change_seq_pmu_setup_exit:
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return status;
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}
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int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g,
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struct nvgpu_clk_slave_freq *vf_point)
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{
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struct nvgpu_pmu *pmu = g->pmu;
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struct nv_pmu_rpc_perf_change_seq_queue_change rpc;
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struct ctrl_perf_change_seq_change_input change_input;
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struct change_seq_pmu *change_seq_pmu = &g->pmu->perf_pmu->changeseq_pmu;
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int status = 0;
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u8 gpcclk_domain = 0U;
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u32 gpcclk_voltuv = 0U, gpcclk_clkmhz = 0U;
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u32 vmin_uv = 0U, vmax_uv = 0U;
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u32 vmargin_uv = 0U, fmargin_mhz = 0U;
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(void) memset(&change_input, 0,
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sizeof(struct ctrl_perf_change_seq_change_input));
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clk_set_p0_clk_per_domain(g, &gpcclk_domain, &gpcclk_clkmhz,
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vf_point, &change_input.clk);
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change_input.pstate_index =
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perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);
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change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE;
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change_input.vf_points_cache_counter = 0xFFFFFFFFU;
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status = nvgpu_pmu_perf_vfe_get_freq_margin(g, &fmargin_mhz);
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if (status != 0) {
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nvgpu_err(g, "Failed to fetch Fmargin status=0x%x", status);
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return status;
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}
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gpcclk_clkmhz += fmargin_mhz;
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status = nvgpu_pmu_clk_domain_freq_to_volt(g, gpcclk_domain,
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&gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);
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status = nvgpu_pmu_perf_vfe_get_volt_margin(g, &vmargin_uv);
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if (status != 0) {
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nvgpu_err(g, "Failed to fetch Vmargin status=0x%x", status);
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return status;
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}
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gpcclk_voltuv += vmargin_uv;
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status = nvgpu_pmu_volt_get_vmin_vmax_ps35(g, &vmin_uv, &vmax_uv);
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if (status != 0) {
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nvgpu_pmu_dbg(g, "Get vmin,vmax failed, proceeding with "
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"freq_to_volt value");
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}
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if ((status == 0) && (vmin_uv > gpcclk_voltuv)) {
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gpcclk_voltuv = vmin_uv;
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nvgpu_log_fn(g, "Vmin is higher than evaluated Volt");
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}
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if (gpcclk_voltuv > vmax_uv) {
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nvgpu_err(g, "Error: Requested voltage is more than chip max");
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return -EINVAL;
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}
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change_input.volt[0].voltage_uv = gpcclk_voltuv;
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change_input.volt[0].voltage_min_noise_unaware_uv = gpcclk_voltuv;
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change_input.volt_rails_mask.super.data[0] = 1U;
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/* RPC to PMU to queue to execute change sequence request*/
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(void) memset(&rpc, 0,
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sizeof(struct nv_pmu_rpc_perf_change_seq_queue_change));
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rpc.change = change_input;
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rpc.change.pstate_index =
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perf_pstate_get_table_entry_idx(g, CTRL_PERF_PSTATE_P0);
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change_seq_pmu->change_state = 0U;
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change_seq_pmu->start_time = nvgpu_current_time_us();
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PMU_RPC_EXECUTE_CPB(status, pmu, PERF,
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CHANGE_SEQ_QUEUE_CHANGE, &rpc, 0);
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if (status != 0) {
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nvgpu_err(g, "Failed to execute Change Seq RPC status=0x%x",
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status);
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}
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/* Wait for sync change to complete. */
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if ((rpc.change.flags & CTRL_PERF_CHANGE_SEQ_CHANGE_ASYNC) == 0U) {
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/* wait till RPC execute in PMU & ACK */
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if (nvgpu_pmu_wait_fw_ack_status(g, pmu,
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nvgpu_get_poll_timeout(g),
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&change_seq_pmu->change_state, 1U) != 0) {
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nvgpu_err(g, "PMU wait timeout expired.");
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status = -ETIMEDOUT;
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}
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}
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change_seq_pmu->stop_time = nvgpu_current_time_us();
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return status;
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}
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void nvgpu_perf_change_seq_execute_time(struct gk20a *g, s64 *change_time)
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{
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struct change_seq_pmu *change_seq_pmu =
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&g->pmu->perf_pmu->changeseq_pmu;
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s64 diff = change_seq_pmu->stop_time - change_seq_pmu->start_time;
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*change_time = diff;
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}
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