Open source GPL/LGPL release

drivers/gpu/nvgpu/common/sec2/ipc/sec2_cmd.c

@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/pmu.h>
+#include <nvgpu/log.h>
+#include <nvgpu/sec2/sec2.h>
+#include <nvgpu/sec2/queue.h>
+#include <nvgpu/sec2/cmd.h>
+
+/* command post operation functions */
+static bool sec2_validate_cmd(struct nvgpu_sec2 *sec2,
+	struct nv_flcn_cmd_sec2 *cmd, u32 queue_id)
+{
+	struct gk20a *g = sec2->g;
+	u32 queue_size;
+
+	if (queue_id != SEC2_NV_CMDQ_LOG_ID) {
+		goto invalid_cmd;
+	}
+
+	if (cmd->hdr.size < PMU_CMD_HDR_SIZE) {
+		goto invalid_cmd;
+	}
+
+	queue_size = nvgpu_sec2_queue_get_size(sec2->queues, queue_id);
+
+	if (cmd->hdr.size > (queue_size >> 1)) {
+		goto invalid_cmd;
+	}
+
+	if (!NV_SEC2_UNITID_IS_VALID(cmd->hdr.unit_id)) {
+		goto invalid_cmd;
+	}
+
+	return true;
+
+invalid_cmd:
+	nvgpu_err(g, "invalid sec2 cmd :");
+	nvgpu_err(g, "queue_id=%d, cmd_size=%d, cmd_unit_id=%d\n",
+		queue_id, cmd->hdr.size, cmd->hdr.unit_id);
+
+	return false;
+}
+
+static int sec2_write_cmd(struct nvgpu_sec2 *sec2,
+	struct nv_flcn_cmd_sec2 *cmd, u32 queue_id,
+	u32 timeout_ms)
+{
+	struct nvgpu_timeout timeout;
+	struct gk20a *g = sec2->g;
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
+
+	do {
+		err = nvgpu_sec2_queue_push(sec2->queues, queue_id, &sec2->flcn,
+					    cmd, cmd->hdr.size);
+		if ((err == -EAGAIN) &&
+		    (nvgpu_timeout_expired(&timeout) == 0)) {
+			nvgpu_usleep_range(1000U, 2000U);
+		} else {
+			break;
+		}
+	} while (true);
+
+	if (err != 0) {
+		nvgpu_err(g, "fail to write cmd to queue %d", queue_id);
+	}
+
+	return err;
+}
+
+int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd,
+	u32 queue_id, sec2_callback callback,
+	void *cb_param, u32 timeout)
+{
+	struct nvgpu_sec2 *sec2 = &g->sec2;
+	struct sec2_sequence *seq = NULL;
+	int err = 0;
+
+	if ((cmd == NULL) || (!sec2->sec2_ready)) {
+		if (cmd == NULL) {
+			nvgpu_warn(g,
+				   "%s(): SEC2 cmd buffer is NULL", __func__);
+		} else {
+			nvgpu_warn(g, "%s(): SEC2 is not ready", __func__);
+		}
+
+		err = -EINVAL;
+		goto exit;
+	}
+
+	/* Sanity check the command input. */
+	if (!sec2_validate_cmd(sec2, cmd, queue_id)) {
+		err = -EINVAL;
+		goto exit;
+	}
+
+	/* Attempt to reserve a sequence for this command. */
+	err = nvgpu_sec2_seq_acquire(g, &sec2->sequences, &seq,
+				     callback, cb_param);
+	if (err != 0) {
+		goto exit;
+	}
+
+	/* Set the sequence number in the command header. */
+	cmd->hdr.seq_id = nvgpu_sec2_seq_get_id(seq);
+
+	cmd->hdr.ctrl_flags = 0U;
+	cmd->hdr.ctrl_flags = PMU_CMD_FLAGS_STATUS;
+
+	nvgpu_sec2_seq_set_state(seq, SEC2_SEQ_STATE_USED);
+
+	err = sec2_write_cmd(sec2, cmd, queue_id, timeout);
+	if (err != 0) {
+		nvgpu_sec2_seq_set_state(seq, SEC2_SEQ_STATE_PENDING);
+	}
+
+exit:
+	return err;
+}

drivers/gpu/nvgpu/common/sec2/ipc/sec2_msg.c

@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/sec2/allocator.h>
+#include <nvgpu/engine_queue.h>
+#include <nvgpu/sec2/queue.h>
+#include <nvgpu/flcnif_cmn.h>
+#include <nvgpu/sec2/sec2.h>
+#include <nvgpu/sec2/msg.h>
+#include <nvgpu/gk20a.h>
+
+/* Message/Event request handlers */
+static int sec2_response_handle(struct nvgpu_sec2 *sec2,
+	struct nv_flcn_msg_sec2 *msg)
+{
+	struct gk20a *g = sec2->g;
+
+	return nvgpu_sec2_seq_response_handle(g, &sec2->sequences,
+					      msg, msg->hdr.seq_id);
+}
+
+static int sec2_handle_event(struct nvgpu_sec2 *sec2,
+	struct nv_flcn_msg_sec2 *msg)
+{
+	int err = 0;
+
+	switch (msg->hdr.unit_id) {
+	default:
+		break;
+	}
+
+	return err;
+}
+
+static bool sec2_read_message(struct nvgpu_sec2 *sec2,
+	u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status)
+{
+	struct gk20a *g = sec2->g;
+	u32 read_size;
+	int err;
+
+	*status = 0U;
+
+	if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) {
+		return false;
+	}
+
+	if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
+				   &sec2->flcn,  &msg->hdr,
+				   PMU_MSG_HDR_SIZE, status)) {
+		nvgpu_err(g, "fail to read msg from queue %d", queue_id);
+		goto clean_up;
+	}
+
+	if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) {
+		err = nvgpu_sec2_queue_rewind(&sec2->flcn,
+					      sec2->queues, queue_id);
+		if (err != 0) {
+			nvgpu_err(g, "fail to rewind queue %d", queue_id);
+			*status = err;
+			goto clean_up;
+		}
+
+		/* read again after rewind */
+		if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
+					   &sec2->flcn, &msg->hdr,
+					   PMU_MSG_HDR_SIZE, status)) {
+			nvgpu_err(g, "fail to read msg from queue %d",
+				queue_id);
+			goto clean_up;
+		}
+	}
+
+	if (!NV_SEC2_UNITID_IS_VALID(msg->hdr.unit_id)) {
+		nvgpu_err(g, "read invalid unit_id %d from queue %d",
+			msg->hdr.unit_id, queue_id);
+			*status = -EINVAL;
+			goto clean_up;
+	}
+
+	if (msg->hdr.size > PMU_MSG_HDR_SIZE) {
+		read_size = msg->hdr.size - PMU_MSG_HDR_SIZE;
+		if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
+					   &sec2->flcn, &msg->msg,
+					   read_size, status)) {
+			nvgpu_err(g, "fail to read msg from queue %d",
+				queue_id);
+			goto clean_up;
+		}
+	}
+
+	return true;
+
+clean_up:
+	return false;
+}
+
+static int sec2_process_init_msg(struct nvgpu_sec2 *sec2,
+	struct nv_flcn_msg_sec2 *msg)
+{
+	struct gk20a *g = sec2->g;
+	struct sec2_init_msg_sec2_init *sec2_init;
+	u32 tail = 0;
+	int err = 0;
+
+	g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET);
+
+	err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail,
+		(u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U);
+	if (err != 0) {
+		goto exit;
+	}
+
+	if (msg->hdr.unit_id != NV_SEC2_UNIT_INIT) {
+		nvgpu_err(g, "expecting init msg");
+		err = -EINVAL;
+		goto exit;
+	}
+
+	err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail + PMU_MSG_HDR_SIZE,
+		(u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U);
+	if (err != 0) {
+		goto exit;
+	}
+
+	if (msg->msg.init.msg_type != NV_SEC2_INIT_MSG_ID_SEC2_INIT) {
+		nvgpu_err(g, "expecting init msg");
+		err = -EINVAL;
+		goto exit;
+	}
+
+	tail += NVGPU_ALIGN(U32(msg->hdr.size), PMU_DMEM_ALIGNMENT);
+	g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET);
+
+	sec2_init = &msg->msg.init.sec2_init;
+
+	err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init);
+	if (err != 0) {
+		return err;
+	}
+
+	err = nvgpu_sec2_dmem_allocator_init(g, &sec2->dmem, sec2_init);
+	if (err != 0) {
+		nvgpu_sec2_queues_free(g, sec2->queues);
+		return err;
+	}
+
+	sec2->sec2_ready = true;
+
+exit:
+	return err;
+}
+
+int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2)
+{
+	struct gk20a *g = sec2->g;
+	struct nv_flcn_msg_sec2 msg;
+	int status = 0;
+
+	if (unlikely(!sec2->sec2_ready)) {
+		status = sec2_process_init_msg(sec2, &msg);
+		goto exit;
+	}
+
+	while (sec2_read_message(sec2,
+		SEC2_NV_MSGQ_LOG_ID, &msg, &status)) {
+
+		nvgpu_sec2_dbg(g, "read msg hdr: ");
+		nvgpu_sec2_dbg(g, "unit_id = 0x%08x, size = 0x%08x",
+			msg.hdr.unit_id, msg.hdr.size);
+		nvgpu_sec2_dbg(g, "ctrl_flags = 0x%08x, seq_id = 0x%08x",
+			msg.hdr.ctrl_flags, msg.hdr.seq_id);
+
+		msg.hdr.ctrl_flags &= ~PMU_CMD_FLAGS_PMU_MASK;
+
+		if (msg.hdr.ctrl_flags == PMU_CMD_FLAGS_EVENT) {
+			sec2_handle_event(sec2, &msg);
+		} else {
+			sec2_response_handle(sec2, &msg);
+		}
+	}
+
+exit:
+	return status;
+}
+
+static void sec2_isr(struct gk20a *g, struct nvgpu_sec2 *sec2)
+{
+	bool recheck = false;
+	u32 intr;
+
+	if (!g->ops.sec2.is_interrupted(sec2)) {
+		return;
+	}
+
+	nvgpu_mutex_acquire(&sec2->isr_mutex);
+	if (!sec2->isr_enabled) {
+		goto exit;
+	}
+
+	intr = g->ops.sec2.get_intr(g);
+	if (intr == 0U) {
+		goto exit;
+	}
+
+	/*
+	 * Handle swgen0 interrupt to process received messages from SEC2.
+	 * If any other interrupt is to be handled with some software
+	 * action expected, then it should be handled here.
+	 * g->ops.sec2.isr call below will handle other hardware interrupts
+	 * that are not expected to be handled in software.
+	 */
+	if (g->ops.sec2.msg_intr_received(g)) {
+		if (nvgpu_sec2_process_message(sec2) != 0) {
+			g->ops.sec2.clr_intr(g, intr);
+			goto exit;
+		}
+		recheck = true;
+	}
+
+	g->ops.sec2.process_intr(g, sec2);
+	g->ops.sec2.clr_intr(g, intr);
+
+	if (recheck) {
+		if (!nvgpu_sec2_queue_is_empty(sec2->queues,
+					       SEC2_NV_MSGQ_LOG_ID)) {
+			g->ops.sec2.set_msg_intr(g);
+		}
+	}
+
+exit:
+	nvgpu_mutex_release(&sec2->isr_mutex);
+}
+
+int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
+	void *var, u8 val)
+{
+	struct gk20a *g = sec2->g;
+	struct nvgpu_timeout timeout;
+	u32 delay = POLL_DELAY_MIN_US;
+
+	nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
+
+	do {
+		if (*(u8 *)var == val) {
+			return 0;
+		}
+
+		sec2_isr(g, sec2);
+
+		nvgpu_usleep_range(delay, delay * 2U);
+		delay = min_t(u32, delay << 1U, POLL_DELAY_MAX_US);
+	} while (nvgpu_timeout_expired(&timeout) == 0);
+
+	return -ETIMEDOUT;
+}

drivers/gpu/nvgpu/common/sec2/ipc/sec2_queue.c

@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/engine_mem_queue.h>
+#include <nvgpu/engine_queue.h>
+#include <nvgpu/sec2/queue.h>
+#include <nvgpu/sec2/msg.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/log.h>
+
+/* sec2 falcon queue init */
+static int sec2_queue_init(struct gk20a *g,
+			   struct nvgpu_engine_mem_queue **queues, u32 id,
+			   struct sec2_init_msg_sec2_init *init)
+{
+	struct nvgpu_engine_mem_queue_params params = {0};
+	u32 queue_log_id = 0;
+	u32 oflag = 0;
+	int err = 0;
+
+	if (id == SEC2_NV_CMDQ_LOG_ID) {
+		/*
+		 * set OFLAG_WRITE for command queue
+		 * i.e, push from nvgpu &
+		 * pop form falcon ucode
+		 */
+		oflag = OFLAG_WRITE;
+	} else if (id == SEC2_NV_MSGQ_LOG_ID) {
+		/*
+		 * set OFLAG_READ for message queue
+		 * i.e, push from falcon ucode &
+		 * pop form nvgpu
+		 */
+		oflag = OFLAG_READ;
+	} else {
+		nvgpu_err(g, "invalid queue-id %d", id);
+		err = -EINVAL;
+		goto exit;
+	}
+
+	/* init queue parameters */
+	queue_log_id = init->q_info[id].queue_log_id;
+
+	params.g = g;
+	params.flcn_id = FALCON_ID_SEC2;
+	params.id = queue_log_id;
+	params.index = init->q_info[id].queue_phy_id;
+	params.offset = init->q_info[id].queue_offset;
+	params.position = init->q_info[id].queue_offset;
+	params.size = init->q_info[id].queue_size;
+	params.oflag = oflag;
+	params.queue_head = g->ops.sec2.sec2_queue_head;
+	params.queue_tail = g->ops.sec2.sec2_queue_tail;
+	params.queue_type = QUEUE_TYPE_EMEM;
+
+	err = nvgpu_engine_mem_queue_init(&queues[queue_log_id],
+				      params);
+	if (err != 0) {
+		nvgpu_err(g, "queue-%d init failed", queue_log_id);
+	}
+
+exit:
+	return err;
+}
+
+static void sec2_queue_free(struct gk20a *g,
+			    struct nvgpu_engine_mem_queue **queues, u32 id)
+{
+	if (!(id == SEC2_NV_CMDQ_LOG_ID) && !(id == SEC2_NV_MSGQ_LOG_ID)) {
+		nvgpu_err(g, "invalid queue-id %d", id);
+		goto exit;
+	}
+
+	if (queues[id] == NULL) {
+		goto exit;
+	}
+
+	nvgpu_engine_mem_queue_free(&queues[id]);
+exit:
+	return;
+}
+
+int nvgpu_sec2_queues_init(struct gk20a *g,
+			   struct nvgpu_engine_mem_queue **queues,
+			   struct sec2_init_msg_sec2_init *init)
+{
+	u32 i, j;
+	int err;
+
+	for (i = 0; i < SEC2_QUEUE_NUM; i++) {
+		err = sec2_queue_init(g, queues, i, init);
+		if (err != 0) {
+			for (j = 0; j < i; j++) {
+				sec2_queue_free(g, queues, j);
+			}
+			nvgpu_err(g, "SEC2 queue init failed");
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+void nvgpu_sec2_queues_free(struct gk20a *g,
+			    struct nvgpu_engine_mem_queue **queues)
+{
+	u32 i;
+
+	for (i = 0; i < SEC2_QUEUE_NUM; i++) {
+		sec2_queue_free(g, queues, i);
+	}
+}
+
+u32 nvgpu_sec2_queue_get_size(struct nvgpu_engine_mem_queue **queues,
+			      u32 queue_id)
+{
+	return nvgpu_engine_mem_queue_get_size(queues[queue_id]);
+}
+
+int nvgpu_sec2_queue_push(struct nvgpu_engine_mem_queue **queues,
+			  u32 queue_id, struct nvgpu_falcon *flcn,
+			  struct nv_flcn_cmd_sec2 *cmd, u32 size)
+{
+	struct nvgpu_engine_mem_queue *queue;
+
+	queue = queues[queue_id];
+	return nvgpu_engine_mem_queue_push(flcn, queue, cmd, size);
+}
+
+bool nvgpu_sec2_queue_is_empty(struct nvgpu_engine_mem_queue **queues,
+			       u32 queue_id)
+{
+	struct nvgpu_engine_mem_queue *queue = queues[queue_id];
+
+	return nvgpu_engine_mem_queue_is_empty(queue);
+}
+
+bool nvgpu_sec2_queue_read(struct gk20a *g,
+			   struct nvgpu_engine_mem_queue **queues,
+			   u32 queue_id, struct nvgpu_falcon *flcn, void *data,
+			   u32 bytes_to_read, int *status)
+{
+	struct nvgpu_engine_mem_queue *queue = queues[queue_id];
+	u32 bytes_read;
+	int err;
+
+	err = nvgpu_engine_mem_queue_pop(flcn, queue, data,
+			bytes_to_read, &bytes_read);
+	if (err != 0) {
+		nvgpu_err(g, "fail to read msg: err %d", err);
+		*status = err;
+		return false;
+	}
+	if (bytes_read != bytes_to_read) {
+		nvgpu_err(g, "fail to read requested bytes: 0x%x != 0x%x",
+			bytes_to_read, bytes_read);
+		*status = -EINVAL;
+		return false;
+	}
+
+	return true;
+}
+
+int nvgpu_sec2_queue_rewind(struct nvgpu_falcon *flcn,
+			    struct nvgpu_engine_mem_queue **queues,
+			    u32 queue_id)
+{
+	struct nvgpu_engine_mem_queue *queue = queues[queue_id];
+
+	return nvgpu_engine_mem_queue_rewind(flcn, queue);
+}

drivers/gpu/nvgpu/common/sec2/ipc/sec2_seq.c

@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/sec2/seq.h>
+#include <nvgpu/string.h>
+#include <nvgpu/kmem.h>
+#include <nvgpu/log.h>
+#include <nvgpu/errno.h>
+
+int nvgpu_sec2_sequences_alloc(struct gk20a *g,
+			       struct sec2_sequences *sequences)
+{
+	sequences->seq = nvgpu_kzalloc(g, SEC2_MAX_NUM_SEQUENCES *
+				       sizeof(struct sec2_sequence));
+	if (sequences->seq == NULL) {
+		return -ENOMEM;
+	}
+
+	nvgpu_mutex_init(&sequences->sec2_seq_lock);
+
+	return 0;
+}
+
+void nvgpu_sec2_sequences_init(struct gk20a *g,
+			       struct sec2_sequences *sequences)
+{
+	u32 i = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	(void) memset(sequences->seq, 0,
+		sizeof(struct sec2_sequence) * SEC2_MAX_NUM_SEQUENCES);
+
+	(void) memset(sequences->sec2_seq_tbl, 0,
+		      sizeof(sequences->sec2_seq_tbl));
+
+	for (i = 0; i < SEC2_MAX_NUM_SEQUENCES; i++) {
+		sequences->seq[i].id = (u8)i;
+	}
+}
+
+void nvgpu_sec2_sequences_free(struct gk20a *g,
+			       struct sec2_sequences *sequences)
+{
+	nvgpu_mutex_destroy(&sequences->sec2_seq_lock);
+	nvgpu_kfree(g, sequences->seq);
+}
+
+int nvgpu_sec2_seq_acquire(struct gk20a *g,
+			   struct sec2_sequences *sequences,
+			   struct sec2_sequence **pseq,
+			   sec2_callback callback, void *cb_params)
+{
+	struct sec2_sequence *seq;
+	u32 index = 0;
+	int err = 0;
+
+	nvgpu_mutex_acquire(&sequences->sec2_seq_lock);
+
+	index = find_first_zero_bit(sequences->sec2_seq_tbl,
+		sizeof(sequences->sec2_seq_tbl));
+
+	if (index >= sizeof(sequences->sec2_seq_tbl)) {
+		nvgpu_err(g, "no free sequence available");
+		nvgpu_mutex_release(&sequences->sec2_seq_lock);
+		err = -EAGAIN;
+		goto exit;
+	}
+
+	nvgpu_assert(index < U64(INT_MAX));
+	nvgpu_set_bit(index, sequences->sec2_seq_tbl);
+
+	nvgpu_mutex_release(&sequences->sec2_seq_lock);
+
+	seq = &sequences->seq[index];
+
+	seq->state = SEC2_SEQ_STATE_PENDING;
+	seq->callback = callback;
+	seq->cb_params = cb_params;
+	seq->out_payload = NULL;
+
+	*pseq = seq;
+
+exit:
+	return err;
+}
+
+static void sec2_seq_release(struct sec2_sequences *sequences,
+			     struct sec2_sequence *seq)
+{
+	seq->state	= SEC2_SEQ_STATE_FREE;
+	seq->callback	= NULL;
+	seq->cb_params	= NULL;
+	seq->out_payload = NULL;
+
+	nvgpu_mutex_acquire(&sequences->sec2_seq_lock);
+	nvgpu_clear_bit(seq->id, sequences->sec2_seq_tbl);
+	nvgpu_mutex_release(&sequences->sec2_seq_lock);
+}
+
+int nvgpu_sec2_seq_response_handle(struct gk20a *g,
+				   struct sec2_sequences *sequences,
+				   struct nv_flcn_msg_sec2 *msg, u32 seq_id)
+{
+	struct sec2_sequence *seq;
+
+	/* get the sequence info data associated with this message */
+	seq = &sequences->seq[seq_id];
+
+
+	if (seq->state != SEC2_SEQ_STATE_USED) {
+		nvgpu_err(g, "msg for an unknown sequence %d", seq->id);
+		return -EINVAL;
+	}
+
+	if (seq->callback != NULL) {
+		seq->callback(g, msg, seq->cb_params, 0);
+	}
+
+	/* release the sequence so that it may be used for other commands */
+	sec2_seq_release(sequences, seq);
+
+	return 0;
+}
+
+u8 nvgpu_sec2_seq_get_id(struct sec2_sequence *seq)
+{
+	return seq->id;
+}
+
+void nvgpu_sec2_seq_set_state(struct sec2_sequence *seq,
+			      enum sec2_seq_state state)
+{
+	seq->state = state;
+}

drivers/gpu/nvgpu/common/sec2/sec2.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/log.h>
+#include <nvgpu/sec2/sec2.h>
+#include <nvgpu/sec2/queue.h>
+#include <nvgpu/sec2/seq.h>
+#include <nvgpu/sec2/allocator.h>
+#include <nvgpu/sec2/msg.h>
+
+static void nvgpu_remove_sec2_support(struct nvgpu_sec2 *sec2)
+{
+	struct gk20a *g = sec2->g;
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_sec2_sequences_free(g, &sec2->sequences);
+	nvgpu_mutex_destroy(&sec2->isr_mutex);
+}
+
+int nvgpu_init_sec2_setup_sw(struct gk20a *g)
+{
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	g->sec2.g = g;
+
+	err = nvgpu_sec2_sequences_alloc(g, &g->sec2.sequences);
+	if (err != 0) {
+		return err;
+	}
+
+	nvgpu_sec2_sequences_init(g, &g->sec2.sequences);
+
+	nvgpu_mutex_init(&g->sec2.isr_mutex);
+
+	g->sec2.remove_support = nvgpu_remove_sec2_support;
+
+	return err;
+}
+
+int nvgpu_init_sec2_support(struct gk20a *g)
+{
+	struct nvgpu_sec2 *sec2 = &g->sec2;
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	/* Enable irq*/
+	nvgpu_mutex_acquire(&sec2->isr_mutex);
+	g->ops.sec2.enable_irq(sec2, true);
+	sec2->isr_enabled = true;
+	nvgpu_mutex_release(&sec2->isr_mutex);
+
+	/* execute SEC2 in secure mode to boot RTOS */
+	g->ops.sec2.secured_sec2_start(g);
+
+	return err;
+}
+
+int nvgpu_sec2_destroy(struct gk20a *g)
+{
+	struct nvgpu_sec2 *sec2 = &g->sec2;
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_sec2_dmem_allocator_destroy(&sec2->dmem);
+
+	nvgpu_mutex_acquire(&sec2->isr_mutex);
+	sec2->isr_enabled = false;
+	nvgpu_mutex_release(&sec2->isr_mutex);
+
+	nvgpu_sec2_queues_free(g, sec2->queues);
+
+	sec2->sec2_ready = false;
+
+	return 0;
+}

drivers/gpu/nvgpu/common/sec2/sec2_allocator.c

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/sec2/allocator.h>
+#include <nvgpu/allocator.h>
+#include <nvgpu/sec2/msg.h>
+
+int nvgpu_sec2_dmem_allocator_init(struct gk20a *g,
+				struct nvgpu_allocator *dmem,
+				struct sec2_init_msg_sec2_init *sec2_init)
+{
+	int err = 0;
+	if (!nvgpu_alloc_initialized(dmem)) {
+		/* Align start and end addresses */
+		u32 start = NVGPU_ALIGN(sec2_init->nv_managed_area_offset,
+			PMU_DMEM_ALLOC_ALIGNMENT);
+
+		u32 end = (sec2_init->nv_managed_area_offset +
+			sec2_init->nv_managed_area_size) &
+			~(PMU_DMEM_ALLOC_ALIGNMENT - 1U);
+		u32 size = end - start;
+
+		err = nvgpu_allocator_init(g, dmem, NULL, "sec2_dmem", start,
+				size, PMU_DMEM_ALLOC_ALIGNMENT, 0ULL, 0ULL,
+				BITMAP_ALLOCATOR);
+		if (err != 0) {
+			nvgpu_err(g, "Couldn't init sec2_dmem allocator\n");
+		}
+	}
+	return err;
+}
+
+void nvgpu_sec2_dmem_allocator_destroy(struct nvgpu_allocator *dmem)
+{
+	if (nvgpu_alloc_initialized(dmem)) {
+		nvgpu_alloc_destroy(dmem);
+	}
+}

drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c

@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/pmu/pmuif/cmn.h>
+#include <nvgpu/sec2/lsfm.h>
+#include <nvgpu/sec2/msg.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/sec2/cmd.h>
+#include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr_utils.h>
+#include <nvgpu/gr/gr_instances.h>
+
+/* Add code below to handle SEC2 RTOS commands */
+/* LSF's bootstrap command */
+static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g,
+	struct nv_flcn_msg_sec2 *msg,
+	void *param, u32 status)
+{
+	bool *command_ack = param;
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_sec2_dbg(g, "reply NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON");
+
+	nvgpu_sec2_dbg(g, "flcn %d: error code = %x",
+		msg->msg.acr.msg_flcn.falcon_id,
+		msg->msg.acr.msg_flcn.error_code);
+
+	*command_ack = true;
+}
+
+static u32 get_gpc_falcon_idx_mask(struct gk20a *g)
+{
+	u32 gpc_falcon_idx_mask = 0U;
+
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		gpc_falcon_idx_mask = nvgpu_grmgr_get_gr_logical_gpc_mask(g,
+			nvgpu_gr_get_cur_instance_id(g));
+	} else {
+		u32 gpc_fs_mask;
+		struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
+
+		gpc_fs_mask = nvgpu_gr_config_get_gpc_mask(gr_config);
+		gpc_falcon_idx_mask =
+			nvgpu_safe_sub_u32(
+			(1U << U32(hweight32(gpc_fs_mask))), 1U);
+	}
+
+	return gpc_falcon_idx_mask;
+}
+
+static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
+	u32 falcon_id, u32 flags)
+{
+	struct nv_flcn_cmd_sec2 cmd;
+	bool command_ack;
+	int err = 0;
+	size_t tmp_size;
+
+	nvgpu_log_fn(g, " ");
+
+	/* send message to load falcon */
+	(void) memset(&cmd, 0, sizeof(struct nv_flcn_cmd_sec2));
+	cmd.hdr.unit_id = NV_SEC2_UNIT_ACR;
+	tmp_size = PMU_CMD_HDR_SIZE +
+		sizeof(struct nv_sec2_acr_cmd_bootstrap_falcon);
+	nvgpu_assert(tmp_size <= U64(U8_MAX));
+	cmd.hdr.size = U8(tmp_size);
+
+	cmd.cmd.acr.bootstrap_falcon.cmd_type =
+		NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON;
+	cmd.cmd.acr.bootstrap_falcon.flags = flags;
+	cmd.cmd.acr.bootstrap_falcon.falcon_id = falcon_id;
+	cmd.cmd.acr.bootstrap_falcon.falcon_instance =
+		nvgpu_grmgr_get_gr_syspipe_id(g,
+			nvgpu_gr_get_cur_instance_id(g));
+	cmd.cmd.acr.bootstrap_falcon.falcon_index_mask =
+		LSF_FALCON_INDEX_MASK_DEFAULT;
+
+	if (falcon_id == FALCON_ID_GPCCS) {
+		cmd.cmd.acr.bootstrap_falcon.falcon_index_mask =
+				get_gpc_falcon_idx_mask(g);
+	}
+
+	nvgpu_sec2_dbg(g, "NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON : %d "
+		"falcon_instance : %u falcon_index_mask : %x",
+		falcon_id,
+		cmd.cmd.acr.bootstrap_falcon.falcon_instance,
+		cmd.cmd.acr.bootstrap_falcon.falcon_index_mask);
+
+	command_ack = false;
+	err = nvgpu_sec2_cmd_post(g, &cmd, PMU_COMMAND_QUEUE_HPQ,
+		sec2_handle_lsfm_boot_acr_msg, &command_ack, U32_MAX);
+	if (err != 0) {
+		nvgpu_err(g, "command post failed");
+	}
+
+	err = nvgpu_sec2_wait_message_cond(sec2, nvgpu_get_poll_timeout(g),
+		&command_ack, U8(true));
+	if (err != 0) {
+		nvgpu_err(g, "command ack receive failed");
+	}
+}
+
+int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
+	u32 falcon_id)
+{
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_sec2_dbg(g, "Check SEC2 RTOS is ready else wait");
+	err = nvgpu_sec2_wait_message_cond(&g->sec2, nvgpu_get_poll_timeout(g),
+			&g->sec2.sec2_ready, U8(true));
+	if (err != 0) {
+		nvgpu_err(g, "SEC2 RTOS not ready yet, failed to bootstrap flcn %d",
+			falcon_id);
+		goto exit;
+	}
+
+	nvgpu_sec2_dbg(g, "LS flcn %d bootstrap, blocked call", falcon_id);
+	sec2_load_ls_falcons(g, sec2, falcon_id,
+		NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES);
+
+exit:
+	nvgpu_sec2_dbg(g, "Done, err-%x", err);
+	return err;
+}