mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 02:22:34 +03:00
Open source GPL/LGPL release
This commit is contained in:
svcmobrel-release
275
drivers/gpu/nvgpu/common/sec2/ipc/sec2_msg.c
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275
drivers/gpu/nvgpu/common/sec2/ipc/sec2_msg.c
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@@ -0,0 +1,275 @@
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/*
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* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/sec2/allocator.h>
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#include <nvgpu/engine_queue.h>
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#include <nvgpu/sec2/queue.h>
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#include <nvgpu/flcnif_cmn.h>
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#include <nvgpu/sec2/sec2.h>
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#include <nvgpu/sec2/msg.h>
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#include <nvgpu/gk20a.h>
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/* Message/Event request handlers */
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static int sec2_response_handle(struct nvgpu_sec2 *sec2,
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struct nv_flcn_msg_sec2 *msg)
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{
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struct gk20a *g = sec2->g;
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return nvgpu_sec2_seq_response_handle(g, &sec2->sequences,
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msg, msg->hdr.seq_id);
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}
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static int sec2_handle_event(struct nvgpu_sec2 *sec2,
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struct nv_flcn_msg_sec2 *msg)
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{
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int err = 0;
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switch (msg->hdr.unit_id) {
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default:
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break;
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}
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return err;
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}
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static bool sec2_read_message(struct nvgpu_sec2 *sec2,
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u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status)
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{
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struct gk20a *g = sec2->g;
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u32 read_size;
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int err;
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*status = 0U;
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if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) {
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return false;
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}
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if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
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&sec2->flcn, &msg->hdr,
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PMU_MSG_HDR_SIZE, status)) {
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nvgpu_err(g, "fail to read msg from queue %d", queue_id);
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goto clean_up;
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}
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if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) {
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err = nvgpu_sec2_queue_rewind(&sec2->flcn,
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sec2->queues, queue_id);
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if (err != 0) {
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nvgpu_err(g, "fail to rewind queue %d", queue_id);
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*status = err;
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goto clean_up;
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}
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/* read again after rewind */
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if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
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&sec2->flcn, &msg->hdr,
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PMU_MSG_HDR_SIZE, status)) {
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nvgpu_err(g, "fail to read msg from queue %d",
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queue_id);
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goto clean_up;
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}
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}
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if (!NV_SEC2_UNITID_IS_VALID(msg->hdr.unit_id)) {
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nvgpu_err(g, "read invalid unit_id %d from queue %d",
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msg->hdr.unit_id, queue_id);
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*status = -EINVAL;
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goto clean_up;
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}
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if (msg->hdr.size > PMU_MSG_HDR_SIZE) {
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read_size = msg->hdr.size - PMU_MSG_HDR_SIZE;
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if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
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&sec2->flcn, &msg->msg,
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read_size, status)) {
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nvgpu_err(g, "fail to read msg from queue %d",
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queue_id);
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goto clean_up;
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}
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}
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return true;
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clean_up:
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return false;
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}
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static int sec2_process_init_msg(struct nvgpu_sec2 *sec2,
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struct nv_flcn_msg_sec2 *msg)
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{
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struct gk20a *g = sec2->g;
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struct sec2_init_msg_sec2_init *sec2_init;
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u32 tail = 0;
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int err = 0;
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g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET);
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err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail,
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(u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U);
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if (err != 0) {
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goto exit;
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}
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if (msg->hdr.unit_id != NV_SEC2_UNIT_INIT) {
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nvgpu_err(g, "expecting init msg");
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err = -EINVAL;
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goto exit;
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}
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err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail + PMU_MSG_HDR_SIZE,
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(u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U);
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if (err != 0) {
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goto exit;
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}
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if (msg->msg.init.msg_type != NV_SEC2_INIT_MSG_ID_SEC2_INIT) {
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nvgpu_err(g, "expecting init msg");
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err = -EINVAL;
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goto exit;
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}
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tail += NVGPU_ALIGN(U32(msg->hdr.size), PMU_DMEM_ALIGNMENT);
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g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET);
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sec2_init = &msg->msg.init.sec2_init;
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err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init);
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if (err != 0) {
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return err;
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}
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err = nvgpu_sec2_dmem_allocator_init(g, &sec2->dmem, sec2_init);
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if (err != 0) {
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nvgpu_sec2_queues_free(g, sec2->queues);
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return err;
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}
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sec2->sec2_ready = true;
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exit:
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return err;
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}
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int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2)
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{
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struct gk20a *g = sec2->g;
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struct nv_flcn_msg_sec2 msg;
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int status = 0;
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if (unlikely(!sec2->sec2_ready)) {
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status = sec2_process_init_msg(sec2, &msg);
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goto exit;
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}
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while (sec2_read_message(sec2,
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SEC2_NV_MSGQ_LOG_ID, &msg, &status)) {
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nvgpu_sec2_dbg(g, "read msg hdr: ");
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nvgpu_sec2_dbg(g, "unit_id = 0x%08x, size = 0x%08x",
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msg.hdr.unit_id, msg.hdr.size);
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nvgpu_sec2_dbg(g, "ctrl_flags = 0x%08x, seq_id = 0x%08x",
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msg.hdr.ctrl_flags, msg.hdr.seq_id);
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msg.hdr.ctrl_flags &= ~PMU_CMD_FLAGS_PMU_MASK;
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if (msg.hdr.ctrl_flags == PMU_CMD_FLAGS_EVENT) {
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sec2_handle_event(sec2, &msg);
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} else {
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sec2_response_handle(sec2, &msg);
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}
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}
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exit:
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return status;
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}
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static void sec2_isr(struct gk20a *g, struct nvgpu_sec2 *sec2)
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{
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bool recheck = false;
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u32 intr;
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if (!g->ops.sec2.is_interrupted(sec2)) {
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return;
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}
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nvgpu_mutex_acquire(&sec2->isr_mutex);
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if (!sec2->isr_enabled) {
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goto exit;
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}
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intr = g->ops.sec2.get_intr(g);
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if (intr == 0U) {
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goto exit;
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}
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/*
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* Handle swgen0 interrupt to process received messages from SEC2.
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* If any other interrupt is to be handled with some software
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* action expected, then it should be handled here.
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* g->ops.sec2.isr call below will handle other hardware interrupts
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* that are not expected to be handled in software.
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*/
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if (g->ops.sec2.msg_intr_received(g)) {
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if (nvgpu_sec2_process_message(sec2) != 0) {
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g->ops.sec2.clr_intr(g, intr);
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goto exit;
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}
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recheck = true;
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}
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g->ops.sec2.process_intr(g, sec2);
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g->ops.sec2.clr_intr(g, intr);
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if (recheck) {
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if (!nvgpu_sec2_queue_is_empty(sec2->queues,
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SEC2_NV_MSGQ_LOG_ID)) {
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g->ops.sec2.set_msg_intr(g);
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}
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}
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exit:
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nvgpu_mutex_release(&sec2->isr_mutex);
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}
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int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
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void *var, u8 val)
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{
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struct gk20a *g = sec2->g;
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struct nvgpu_timeout timeout;
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u32 delay = POLL_DELAY_MIN_US;
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nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
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do {
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if (*(u8 *)var == val) {
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return 0;
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}
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sec2_isr(g, sec2);
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nvgpu_usleep_range(delay, delay * 2U);
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delay = min_t(u32, delay << 1U, POLL_DELAY_MAX_US);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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return -ETIMEDOUT;
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}
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