mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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Open source GPL/LGPL release
This commit is contained in:
svcmobrel-release
269
drivers/gpu/nvgpu/common/sim/sim_pci.c
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269
drivers/gpu/nvgpu/common/sim/sim_pci.c
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/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/bitops.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/hw_sim_pci.h>
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#include <nvgpu/sim.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/string.h>
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static inline u32 pci_sim_msg_header_size(void)
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{
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return 32U;
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}
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static inline u32 *pci_sim_msg_param(struct gk20a *g, u32 byte_offset)
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{
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/* starts after msg header/cmn */
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return sim_msg_bfr(g, byte_offset + pci_sim_msg_header_size());
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}
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static inline void pci_sim_write_hdr(struct gk20a *g, u32 func, u32 size)
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{
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*sim_msg_hdr(g, sim_msg_header_version_r()) =
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sim_msg_header_version_major_tot_v() |
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sim_msg_header_version_minor_tot_v();
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*sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
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*sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
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*sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
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*sim_msg_hdr(g, sim_msg_function_r()) = func;
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*sim_msg_hdr(g, sim_msg_length_r()) =
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size + pci_sim_msg_header_size();
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}
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static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
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{
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u8 *cpu_va;
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cpu_va = (u8 *)g->sim->send_bfr.cpu_va;
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return (u32 *)(cpu_va + byte_offset);
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}
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static int rpc_send_message(struct gk20a *g)
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{
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/* calculations done in units of u32s */
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u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
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u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
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u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
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*sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
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sim_dma_target_phys_pci_coherent_f() |
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sim_dma_status_valid_f() |
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sim_dma_size_4kb_f() |
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sim_dma_addr_lo_f(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)
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>> sim_dma_addr_lo_b());
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*sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
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u64_hi32(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr));
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*sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
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g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32)) %
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SIM_BFR_SIZE;
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/* Update the put pointer. This will trap into the host. */
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sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
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return 0;
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}
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static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
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{
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u8 *cpu_va;
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cpu_va = (u8 *)g->sim->recv_bfr.cpu_va;
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return (u32 *)(cpu_va + byte_offset);
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}
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static int rpc_recv_poll(struct gk20a *g)
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{
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u64 recv_phys_addr;
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/* Poll the recv ring get pointer in an infinite loop */
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do {
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g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
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} while (g->sim->recv_ring_put == g->sim->recv_ring_get);
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/* process all replies */
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while (g->sim->recv_ring_put != g->sim->recv_ring_get) {
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/* these are in u32 offsets */
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u32 dma_lo_offset =
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sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0;
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u32 dma_hi_offset = dma_lo_offset + 1;
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u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
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*sim_recv_ring_bfr(g, dma_lo_offset*4));
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u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
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*sim_recv_ring_bfr(g, dma_hi_offset*4));
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recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
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(u64)recv_phys_addr_lo << sim_dma_addr_lo_b();
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if (recv_phys_addr !=
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nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)) {
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nvgpu_err(g, "Error in RPC reply");
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return -EINVAL;
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}
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/* Update GET pointer */
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g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32))
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% SIM_BFR_SIZE;
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sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
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g->sim->recv_ring_put = sim_readl(g->sim, sim_recv_put_r());
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}
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return 0;
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}
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static int pci_issue_rpc_and_wait(struct gk20a *g)
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{
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int err;
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err = rpc_send_message(g);
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if (err != 0) {
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nvgpu_err(g, "failed rpc_send_message");
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return err;
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}
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err = rpc_recv_poll(g);
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if (err != 0) {
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nvgpu_err(g, "failed rpc_recv_poll");
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return err;
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}
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/* Now check if RPC really succeeded */
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if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) {
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nvgpu_err(g, "received failed status!");
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return -EINVAL;
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}
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return 0;
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}
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static void nvgpu_sim_esc_readl(struct gk20a *g,
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const char *path, u32 index, u32 *data)
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{
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int err;
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size_t pathlen = strlen(path);
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u32 data_offset;
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pci_sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
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sim_escape_read_hdr_size());
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*pci_sim_msg_param(g, 0) = index;
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*pci_sim_msg_param(g, 4) = sizeof(u32);
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data_offset = round_up(pathlen + 1, sizeof(u32));
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*pci_sim_msg_param(g, 8) = data_offset;
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strcpy((char *)pci_sim_msg_param(g, sim_escape_read_hdr_size()), path);
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err = pci_issue_rpc_and_wait(g);
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if (err == 0) {
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nvgpu_memcpy((u8 *)data,
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(u8 *)pci_sim_msg_param(g,
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nvgpu_safe_add_u32(data_offset,
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sim_escape_read_hdr_size())),
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sizeof(u32));
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} else {
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*data = 0xffffffff;
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WARN(1, "pci_issue_rpc_and_wait failed err=%d", err);
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}
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}
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static int nvgpu_sim_init_late(struct gk20a *g)
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{
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u64 phys;
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int err = -ENOMEM;
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nvgpu_info(g, "sim init late pci");
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if (!g->sim) {
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return 0;
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}
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/* allocate sim event/msg buffers */
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err = nvgpu_alloc_sim_buffer(g, &g->sim->send_bfr);
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err = err || nvgpu_alloc_sim_buffer(g, &g->sim->recv_bfr);
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err = err || nvgpu_alloc_sim_buffer(g, &g->sim->msg_bfr);
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if (err != 0) {
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goto fail;
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}
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/* mark send ring invalid */
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sim_writel(g->sim, sim_send_ring_r(), sim_send_ring_status_invalid_f());
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/* read get pointer and make equal to put */
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g->sim->send_ring_put = sim_readl(g->sim, sim_send_get_r());
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sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
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/* write send ring address and make it valid */
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phys = nvgpu_mem_get_phys_addr(g, &g->sim->send_bfr);
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sim_writel(g->sim, sim_send_ring_hi_r(),
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sim_send_ring_hi_addr_f(u64_hi32(phys)));
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sim_writel(g->sim, sim_send_ring_r(),
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sim_send_ring_status_valid_f() |
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sim_send_ring_target_phys_pci_coherent_f() |
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sim_send_ring_size_4kb_f() |
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sim_send_ring_addr_lo_f(phys >> sim_send_ring_addr_lo_b()));
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/* repeat for recv ring (but swap put,get as roles are opposite) */
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sim_writel(g->sim, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
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/* read put pointer and make equal to get */
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g->sim->recv_ring_get = sim_readl(g->sim, sim_recv_put_r());
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sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
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/* write send ring address and make it valid */
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phys = nvgpu_mem_get_phys_addr(g, &g->sim->recv_bfr);
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sim_writel(g->sim, sim_recv_ring_hi_r(),
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sim_recv_ring_hi_addr_f(u64_hi32(phys)));
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sim_writel(g->sim, sim_recv_ring_r(),
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sim_recv_ring_status_valid_f() |
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sim_recv_ring_target_phys_pci_coherent_f() |
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sim_recv_ring_size_4kb_f() |
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sim_recv_ring_addr_lo_f(phys >> sim_recv_ring_addr_lo_b()));
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return 0;
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fail:
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nvgpu_free_sim_support(g);
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return err;
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}
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int nvgpu_init_sim_support_pci(struct gk20a *g)
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{
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if(!g->sim) {
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return 0;
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}
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g->sim->sim_init_late = nvgpu_sim_init_late;
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g->sim->remove_support = nvgpu_remove_sim_support;
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g->sim->esc_readl = nvgpu_sim_esc_readl;
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return 0;
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}
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