mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-25 11:04:51 +03:00
Open source GPL/LGPL release
This commit is contained in:
svcmobrel-release
309
drivers/gpu/nvgpu/common/vgpu/clk_vgpu.c
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309
drivers/gpu/nvgpu/common/vgpu/clk_vgpu.c
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@@ -0,0 +1,309 @@
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/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/clk_arb.h>
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#include <nvgpu/pmu/clk/clk.h>
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#include "clk_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
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int err;
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unsigned long ret = 0;
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nvgpu_log_fn(g, " ");
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_SYSCLK:
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case CTRL_CLK_DOMAIN_GPCCLK:
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msg.cmd = TEGRA_VGPU_CMD_GET_GPU_CLK_RATE;
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msg.handle = vgpu_get_handle(g);
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(g, "%s failed - %d", __func__, err);
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} else {
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/* return frequency in Hz */
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ret = p->rate;
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}
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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nvgpu_err(g, "unsupported clock: %u", api_domain);
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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break;
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}
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return ret;
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}
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static int vgpu_clk_set_rate(struct gk20a *g,
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u32 api_domain, unsigned long rate)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
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int err = -EINVAL;
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nvgpu_log_fn(g, " ");
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE;
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msg.handle = vgpu_get_handle(g);
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p->rate = rate;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(g, "%s failed - %d", __func__, err);
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}
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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nvgpu_err(g, "unsupported clock: %u", api_domain);
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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break;
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}
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return err;
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}
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static unsigned long vgpu_clk_get_maxrate(struct gk20a *g, u32 api_domain)
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{
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unsigned long *freqs;
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int num_freqs = 0;
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int err;
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unsigned long ret = 0;
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nvgpu_log_fn(g, " ");
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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err = vgpu_clk_get_freqs(g, &freqs, &num_freqs);
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if (err == 0) {
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/* return freq in Hz */
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ret = freqs[num_freqs - 1];
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}
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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break;
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}
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return ret;
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}
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static int vgpu_clk_get_round_rate(struct gk20a *g, u32 api_domain,
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unsigned long rate_target, unsigned long *rounded_rate)
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{
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int err = -EINVAL;
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nvgpu_log_fn(g, " ");
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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*rounded_rate = rate_target;
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err = 0;
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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break;
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}
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return err;
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}
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static int vgpu_clk_get_range(struct gk20a *g, u32 api_domain,
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u16 *min_mhz, u16 *max_mhz)
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{
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unsigned long *freqs;
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int num_freqs = 0;
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int err = -EINVAL;
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nvgpu_log_fn(g, " ");
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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err = vgpu_clk_get_freqs(g, &freqs, &num_freqs);
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if (err == 0) {
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/* return freq in MHz */
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*min_mhz = (u16)(freqs[0] / 1000000);
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*max_mhz = (u16)(freqs[num_freqs - 1] / 1000000);
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}
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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break;
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}
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return err;
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}
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static int vgpu_clk_get_f_points(struct gk20a *g,
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u32 api_domain, u32 *num_points, u16 *freqs_mhz)
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{
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unsigned long *freqs;
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int num_freqs = 0;
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u32 i;
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int err = -EINVAL;
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nvgpu_log_fn(g, " ");
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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err = vgpu_clk_get_freqs(g, &freqs, &num_freqs);
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if (err) {
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return err;
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}
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if (num_points == NULL) {
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return -EINVAL;
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}
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if (*num_points != 0U) {
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if (freqs == NULL || (*num_points > (u32)num_freqs)) {
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return -EINVAL;
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}
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}
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if (*num_points == 0) {
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*num_points = num_freqs;
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} else {
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for (i = 0; i < *num_points; i++) {
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/* return freq in MHz */
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freqs_mhz[i] = (u16)(freqs[i] / 1000000);
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}
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}
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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break;
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}
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return err;
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}
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void vgpu_init_clk_support(struct gk20a *g)
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{
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g->ops.clk.get_rate = vgpu_clk_get_rate;
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g->ops.clk.set_rate = vgpu_clk_set_rate;
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g->ops.clk.get_maxrate = vgpu_clk_get_maxrate;
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g->ops.clk.clk_get_round_rate = vgpu_clk_get_round_rate;
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g->ops.clk.get_clk_range = vgpu_clk_get_range;
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g->ops.clk.clk_domain_get_f_points = vgpu_clk_get_f_points;
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g->ops.clk.measure_freq = nvgpu_clk_measure_freq;
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}
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int vgpu_clk_get_freqs(struct gk20a *g, unsigned long **freqs_out,
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int *num_freqs)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_get_gpu_freq_table_params *p =
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&msg.params.get_gpu_freq_table;
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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u64 *freqs;
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int err = 0;
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void *handle = NULL;
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size_t oob_size;
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unsigned int i;
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nvgpu_log_fn(g, " ");
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nvgpu_mutex_acquire(&priv->vgpu_clk_get_freq_lock);
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if (priv->freqs != NULL) {
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goto done;
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}
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msg.cmd = TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE;
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msg.handle = vgpu_get_handle(g);
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(g, "%s failed - %d", __func__, err);
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goto done;
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}
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handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
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TEGRA_VGPU_QUEUE_CMD, (void **)&freqs, &oob_size);
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if (!handle) {
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nvgpu_err(g, "failed to get ivm handle");
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err = -EINVAL;
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goto done;
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}
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priv->freqs = nvgpu_kzalloc(g, sizeof(*priv->freqs) * (p->num_freqs));
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if (!priv->freqs) {
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nvgpu_err(g, "failed to allocate memory");
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vgpu_ivc_oob_put_ptr(handle);
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err = -ENOMEM;
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goto done;
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}
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priv->num_freqs = p->num_freqs;
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for (i = 0; i < priv->num_freqs; i++) {
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/* store frequency in Hz */
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priv->freqs[i] = (unsigned long)(freqs[i]);
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}
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vgpu_ivc_oob_put_ptr(handle);
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done:
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if (err == 0) {
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*num_freqs = priv->num_freqs;
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*freqs_out = priv->freqs;
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}
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nvgpu_mutex_release(&priv->vgpu_clk_get_freq_lock);
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return err;
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}
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int vgpu_clk_cap_rate(struct gk20a *g, unsigned long rate)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
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int err = 0;
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nvgpu_log_fn(g, " ");
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msg.cmd = TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE;
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msg.handle = vgpu_get_handle(g);
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p->rate = rate;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(g, "%s failed - %d", __func__, err);
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return err;
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}
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return 0;
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}
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