Open source GPL/LGPL release

drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+
+#include "hal/fifo/ramin_gk20a.h"
+
+#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
+
+void gk20a_ramin_set_gr_ptr(struct gk20a *g,
+		struct nvgpu_mem *inst_block, u64 gpu_va)
+{
+	u32 addr_lo = u64_lo32(gpu_va) >> ram_in_base_shift_v();
+	u32 addr_hi = u64_hi32(gpu_va);
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_gr_wfi_target_w(),
+		 ram_in_gr_cs_wfi_f() | ram_in_gr_wfi_mode_virtual_f() |
+		 ram_in_gr_wfi_ptr_lo_f(addr_lo));
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_gr_wfi_ptr_hi_w(),
+		 ram_in_gr_wfi_ptr_hi_f(addr_hi));
+}
+
+void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
+		u64 pdb_addr, struct nvgpu_mem *pdb_mem)
+{
+	u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
+	u32 pdb_addr_hi = u64_hi32(pdb_addr);
+
+	nvgpu_log_info(g, "pde pa=0x%llx", pdb_addr);
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
+		       nvgpu_aperture_mask(g, pdb_mem,
+				ram_in_page_dir_base_target_sys_mem_ncoh_f(),
+				ram_in_page_dir_base_target_sys_mem_coh_f(),
+				ram_in_page_dir_base_target_vid_mem_f()) |
+		       ram_in_page_dir_base_vol_true_f() |
+		       ram_in_page_dir_base_lo_f(pdb_addr_lo));
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
+		ram_in_page_dir_base_hi_f(pdb_addr_hi));
+}
+
+void gk20a_ramin_set_adr_limit(struct gk20a *g,
+		struct nvgpu_mem *inst_block, u64 va_limit)
+{
+	nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(),
+		u64_lo32(va_limit - 1U) & ~0xfffU);
+
+	nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(),
+		ram_in_adr_limit_hi_f(u64_hi32(va_limit - 1U)));
+}