mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 09:57:08 +03:00
Open source GPL/LGPL release
This commit is contained in:
svcmobrel-release
307
drivers/gpu/nvgpu/os/linux/clk.c
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307
drivers/gpu/nvgpu/os/linux/clk.c
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/*
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* Linux clock support
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*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#ifdef CONFIG_TEGRA_DVFS
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#include <soc/tegra/tegra-dvfs.h>
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#endif /* CONFIG_TEGRA_DVFS */
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#ifdef CONFIG_NV_TEGRA_BPMP
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#include <soc/tegra/tegra-bpmp-dvfs.h>
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#endif /* CONFIG_NV_TEGRA_BPMP */
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#include <nvgpu/pmu/clk/clk.h>
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#include "clk.h"
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#include "os_linux.h"
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#include "platform_gk20a.h"
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#include <nvgpu/gk20a.h>
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#include <nvgpu/clk_arb.h>
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#define HZ_TO_MHZ(x) ((x) / 1000000)
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static unsigned long nvgpu_linux_clk_get_rate(struct gk20a *g, u32 api_domain)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
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unsigned long ret;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_SYSCLK:
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case CTRL_CLK_DOMAIN_GPCCLK:
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if (g->clk.tegra_clk)
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ret = clk_get_rate(g->clk.tegra_clk);
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else
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ret = clk_get_rate(platform->clk[0]);
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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ret = clk_get_rate(platform->clk[1]);
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = 0;
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break;
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}
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return ret;
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}
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static int nvgpu_linux_clk_set_rate(struct gk20a *g,
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u32 api_domain, unsigned long rate)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
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int ret;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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if (g->clk.tegra_clk)
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ret = clk_set_rate(g->clk.tegra_clk, rate);
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else
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ret = clk_set_rate(platform->clk[0], rate);
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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ret = clk_set_rate(platform->clk[1], rate);
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
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#ifdef CONFIG_TEGRA_DVFS
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/*
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* On Tegra platforms with GPCPLL bus (gbus) GPU tegra_clk clock exposed
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* to frequency governor is a shared user on the gbus. The latter can be
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* accessed as GPU clock parent, and incorporate DVFS related data.
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*/
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if (g->clk.tegra_clk)
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return tegra_dvfs_get_fmax_at_vmin_safe_t(
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g->clk.tegra_clk_parent);
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#endif
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if (platform->maxmin_clk_id) {
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#ifdef CONFIG_NV_TEGRA_BPMP
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return tegra_bpmp_dvfs_get_fmax_at_vmin(
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platform->maxmin_clk_id);
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#endif
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}
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return 0;
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}
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static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g)
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{
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struct clk *c;
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c = clk_get_sys("gpu_ref", "gpu_ref");
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if (IS_ERR(c)) {
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nvgpu_err(g, "failed to get GPCPLL reference clock");
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return 0;
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}
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return clk_get_rate(c);
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}
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static int nvgpu_linux_predict_mv_at_hz_cur_tfloor(struct clk_gk20a *clk,
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unsigned long rate)
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{
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#ifdef CONFIG_TEGRA_DVFS
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return tegra_dvfs_predict_mv_at_hz_cur_tfloor(
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clk->tegra_clk_parent, rate);
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#else
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return -EINVAL;
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#endif
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}
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static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain)
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{
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int ret;
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u16 min_mhz, max_mhz;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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#ifdef CONFIG_TEGRA_DVFS
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ret = tegra_dvfs_get_maxrate(g->clk.tegra_clk_parent);
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#else
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ret = 0;
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#endif
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/* If dvfs not supported */
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if (ret == 0) {
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int err = nvgpu_clk_arb_get_arbiter_clk_range(g,
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NVGPU_CLK_DOMAIN_GPCCLK,
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&min_mhz, &max_mhz);
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if (err == 0) {
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ret = max_mhz * 1000000L;
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}
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}
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = 0;
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break;
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}
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return ret;
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}
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/*
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* This API is used to return a list of supported frequencies by igpu.
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* Set *num_points as 0 to get the size of the freqs list, returned
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* by *num_points itself. freqs array must be provided by caller.
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* If *num_points is non-zero, then freqs array size must atleast
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* equal *num_points.
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*/
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static int nvgpu_linux_clk_get_f_points(struct gk20a *g,
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u32 api_domain, u32 *num_points, u16 *freqs)
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{
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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unsigned long *gpu_freq_table;
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int ret = 0;
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int num_supported_freq = 0;
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u32 i;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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ret = platform->get_clk_freqs(dev, &gpu_freq_table,
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&num_supported_freq);
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if (ret) {
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return ret;
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}
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if (num_points == NULL) {
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return -EINVAL;
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}
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if (*num_points != 0U) {
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if (freqs == NULL || (*num_points > (u32)num_supported_freq)) {
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return -EINVAL;
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}
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}
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if (*num_points == 0) {
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*num_points = num_supported_freq;
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} else {
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for (i = 0; i < *num_points; i++) {
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freqs[i] = HZ_TO_MHZ(gpu_freq_table[i]);
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}
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}
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int nvgpu_clk_get_range(struct gk20a *g, u32 api_domain,
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u16 *min_mhz, u16 *max_mhz)
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{
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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unsigned long *freqs;
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int num_freqs;
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int ret;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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ret = platform->get_clk_freqs(dev, &freqs, &num_freqs);
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if (!ret) {
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*min_mhz = HZ_TO_MHZ(freqs[0]);
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*max_mhz = HZ_TO_MHZ(freqs[num_freqs - 1]);
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}
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/* rate_target should be passed in as Hz
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rounded_rate is returned in Hz */
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static int nvgpu_clk_get_round_rate(struct gk20a *g,
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u32 api_domain, unsigned long rate_target,
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unsigned long *rounded_rate)
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{
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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unsigned long *freqs;
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int num_freqs;
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int i, ret = 0;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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ret = platform->get_clk_freqs(dev, &freqs, &num_freqs);
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for (i = 0; i < num_freqs; ++i) {
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if (freqs[i] >= rate_target) {
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*rounded_rate = freqs[i];
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return 0;
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}
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}
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*rounded_rate = freqs[num_freqs - 1];
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int nvgpu_linux_prepare_enable(struct clk_gk20a *clk)
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{
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return clk_prepare_enable(clk->tegra_clk);
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}
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static void nvgpu_linux_disable_unprepare(struct clk_gk20a *clk)
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{
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clk_disable_unprepare(clk->tegra_clk);
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}
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void nvgpu_linux_init_clk_support(struct gk20a *g)
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{
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g->ops.clk.get_rate = nvgpu_linux_clk_get_rate;
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g->ops.clk.set_rate = nvgpu_linux_clk_set_rate;
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g->ops.clk.get_fmax_at_vmin_safe = nvgpu_linux_get_fmax_at_vmin_safe;
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g->ops.clk.get_ref_clock_rate = nvgpu_linux_get_ref_clock_rate;
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g->ops.clk.predict_mv_at_hz_cur_tfloor = nvgpu_linux_predict_mv_at_hz_cur_tfloor;
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g->ops.clk.get_maxrate = nvgpu_linux_get_maxrate;
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g->ops.clk.prepare_enable = nvgpu_linux_prepare_enable;
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g->ops.clk.disable_unprepare = nvgpu_linux_disable_unprepare;
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g->ops.clk.clk_domain_get_f_points = nvgpu_linux_clk_get_f_points;
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g->ops.clk.get_clk_range = nvgpu_clk_get_range;
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g->ops.clk.clk_get_round_rate = nvgpu_clk_get_round_rate;
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g->ops.clk.measure_freq = nvgpu_clk_measure_freq;
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}
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