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git://nv-tegra.nvidia.com/linux-nvgpu.git
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Open source GPL/LGPL release
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svcmobrel-release
359
drivers/gpu/nvgpu/os/linux/platform_gk20a.h
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359
drivers/gpu/nvgpu/os/linux/platform_gk20a.h
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/*
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* GK20A Platform (SoC) Interface
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*
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* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GK20A_PLATFORM_H_
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#define _GK20A_PLATFORM_H_
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#include <linux/device.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/gk20a.h>
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#define GK20A_CLKS_MAX 4
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struct gk20a;
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struct nvgpu_channel;
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struct gr_ctx_buffer_desc;
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struct gk20a_scale_profile;
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struct secure_page_buffer {
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void (*destroy)(struct gk20a *, struct secure_page_buffer *);
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size_t size;
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dma_addr_t phys;
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size_t used;
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};
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enum {
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PCI_GPIO_VBAT_PWR_ON,
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PCI_GPIO_PRSNT2,
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PCI_GPIO_PRSNT1,
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PCI_GPIO_PWR_ON,
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PCI_GPIO_PG,
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PCI_GPIO_MAX,
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};
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struct nvgpu_pci_gpios {
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int gpios[PCI_GPIO_MAX];
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};
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/* delays in milliseconds (ms) */
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#define PCI_VBAR_PWR_ON_DELAY_MS 15
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#define PCI_PWR_ON_DELAY_MS 250
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#define PCI_VBAR_PWR_OFF_DELAY_MS 2
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#define PCI_PWR_OFF_DELAY_MS 2
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enum tegra_chip_id {
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TEGRA_124,
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TEGRA_132,
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TEGRA_210,
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TEGRA_186,
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TEGRA_194,
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TEGRA_194_VGPU,
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TEGRA_234,
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};
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struct gk20a_platform {
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/* Populated by the gk20a driver before probing the platform. */
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struct gk20a *g;
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/* Should be populated at probe. */
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bool can_railgate_init;
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/* controls gc off feature for pci gpu */
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bool can_pci_gc_off;
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/* Should be populated at probe. */
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bool can_tpc_powergate;
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/* Should be populated at probe. */
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bool can_elpg_init;
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/* Should be populated at probe. */
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bool has_syncpoints;
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/* channel limit after which to start aggressive sync destroy */
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unsigned int aggressive_sync_destroy_thresh;
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/* set if ASPM should be disabled on boot; only makes sense for PCI */
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bool disable_aspm;
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/* Set if the platform can unify the small/large address spaces. */
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bool unify_address_spaces;
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/* P-state */
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bool pstate;
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/* Clock configuration is stored here. Platform probe is responsible
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* for filling this data. */
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struct clk *clk[GK20A_CLKS_MAX];
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int num_clks;
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int maxmin_clk_id;
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#ifdef CONFIG_RESET_CONTROLLER
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/* Reset control for device */
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struct reset_control *reset_control;
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#endif
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/* valid TPC-MASK */
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u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];
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/* Delay before rail gated */
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int railgate_delay_init;
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/* init value for slowdown factor */
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u8 ldiv_slowdown_factor_init;
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/* Second Level Clock Gating: true = enable false = disable */
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bool enable_slcg;
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/* Block Level Clock Gating: true = enable flase = disable */
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bool enable_blcg;
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/* Engine Level Clock Gating: true = enable flase = disable */
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bool enable_elcg;
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/* Should be populated at probe. */
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bool can_slcg;
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/* Should be populated at probe. */
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bool can_blcg;
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/* Should be populated at probe. */
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bool can_elcg;
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/* Engine Level Power Gating: true = enable flase = disable */
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bool enable_elpg;
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/* Memory System power Gating: true = enable false = disable*/
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bool enable_elpg_ms;
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/* Adaptative ELPG: true = enable flase = disable */
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bool enable_aelpg;
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/* PMU Perfmon: true = enable false = disable */
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bool enable_perfmon;
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/* Memory System Clock Gating: true = enable flase = disable*/
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bool enable_mscg;
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/* Timeout for per-channel watchdog (in mS) */
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u32 ch_wdt_init_limit_ms;
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/* Disable big page support */
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bool disable_bigpage;
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/* Disable nvlink support */
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bool disable_nvlink;
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/* guest/vm id, needed for IPA to PA transation */
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int vmid;
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/* Initialize the platform interface of the gk20a driver.
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*
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* The platform implementation of this function must
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* - set the power and clocks of the gk20a device to a known
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* state, and
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* - populate the gk20a_platform structure (a pointer to the
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* structure can be obtained by calling gk20a_get_platform).
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*
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* After this function is finished, the driver will initialise
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* pm runtime and genpd based on the platform configuration.
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*/
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int (*probe)(struct device *dev);
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/* Second stage initialisation - called once all power management
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* initialisations are done.
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*/
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int (*late_probe)(struct device *dev);
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/* Remove device after power management has been done
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*/
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int (*remove)(struct device *dev);
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/* Poweron platform dependencies */
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int (*busy)(struct device *dev);
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/* Powerdown platform dependencies */
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void (*idle)(struct device *dev);
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/* Preallocated VPR buffer for kernel */
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size_t secure_buffer_size;
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struct secure_page_buffer secure_buffer;
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/* Device is going to be suspended */
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int (*suspend)(struct device *);
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/* Device is going to be resumed */
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int (*resume)(struct device *);
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/* Called to turn off the device */
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int (*railgate)(struct device *dev);
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/* Called to turn on the device */
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int (*unrailgate)(struct device *dev);
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struct nvgpu_mutex railgate_lock;
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/* Called to check state of device */
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bool (*is_railgated)(struct device *dev);
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/* get supported frequency list */
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int (*get_clk_freqs)(struct device *pdev,
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unsigned long **freqs, int *num_freqs);
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/* clk related supported functions */
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long (*clk_round_rate)(struct device *dev,
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unsigned long rate);
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/* Called to register GPCPLL with common clk framework */
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int (*clk_register)(struct gk20a *g);
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/* platform specific scale init quirks */
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void (*initscale)(struct device *dev);
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/* Postscale callback is called after frequency change */
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void (*postscale)(struct device *dev,
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unsigned long freq);
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/* Pre callback is called before frequency change */
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void (*prescale)(struct device *dev);
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/* Set TPC_PG_MASK during probe */
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void (*set_tpc_pg_mask)(struct device *dev, u32 tpc_pg_mask);
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/* Devfreq governor name. If scaling is enabled, we request
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* this governor to be used in scaling */
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const char *devfreq_governor;
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/* Quality of service notifier callback. If this is set, the scaling
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* routines will register a callback to Qos. Each time we receive
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* a new value, this callback gets called. */
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int (*qos_notify)(struct notifier_block *nb,
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unsigned long n, void *p);
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/* Called as part of debug dump. If the gpu gets hung, this function
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* is responsible for delivering all necessary debug data of other
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* hw units which may interact with the gpu without direct supervision
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* of the CPU.
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*/
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void (*dump_platform_dependencies)(struct device *dev);
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/* Defined when SMMU stage-2 is enabled, and we need to use physical
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* addresses (not IPA). This is the case for GV100 nvlink in HV+L
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* configuration, when dGPU is in pass-through mode.
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*/
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u64 (*phys_addr)(struct gk20a *g, u64 ipa, u64 *pa_len);
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/* Callbacks to assert/deassert GPU reset */
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int (*reset_assert)(struct device *dev);
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int (*reset_deassert)(struct device *dev);
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struct clk *clk_reset;
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struct dvfs_rail *gpu_rail;
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bool virtual_dev;
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#ifdef CONFIG_NVGPU_GR_VIRTUALIZATION
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void *vgpu_priv;
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#endif
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/* source frequency for ptimer in hz */
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u32 ptimer_src_freq;
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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bool has_cde;
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#endif
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enum tegra_chip_id platform_chip_id;
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/* soc name for finding firmware files */
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const char *soc_name;
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/* false if vidmem aperture actually points to sysmem */
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bool honors_aperture;
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/* unified or split memory with separate vidmem? */
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bool unified_memory;
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/* Fix for gm20b chips. */
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bool force_128K_pmu_vm;
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/*
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* DMA mask for Linux (both coh and non-coh). If not set defaults to
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* 0x3ffffffff (i.e a 34 bit mask).
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*/
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u64 dma_mask;
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/* true if we run preos microcode on this board */
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bool run_preos;
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/* true if we need to program sw threshold for
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* power limits
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*/
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bool hardcode_sw_threshold;
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/* i2c device index, port and address for INA3221 */
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u32 ina3221_dcb_index;
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u32 ina3221_i2c_address;
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u32 ina3221_i2c_port;
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/* stream id to use */
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u32 ltc_streamid;
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/* synchronized access to platform->clk_get_freqs */
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struct nvgpu_mutex clk_get_freq_lock;
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};
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static inline struct gk20a_platform *gk20a_get_platform(
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struct device *dev)
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{
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return (struct gk20a_platform *)dev_get_drvdata(dev);
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}
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#ifdef CONFIG_TEGRA_GK20A
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extern struct gk20a_platform gm20b_tegra_platform;
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extern struct gk20a_platform gp10b_tegra_platform;
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extern struct gk20a_platform gv11b_tegra_platform;
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#ifdef CONFIG_NVGPU_GR_VIRTUALIZATION
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extern struct gk20a_platform gv11b_vgpu_tegra_platform;
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#endif
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#endif
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int gk20a_tegra_busy(struct device *dev);
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void gk20a_tegra_idle(struct device *dev);
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void gk20a_tegra_debug_dump(struct device *pdev);
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static inline struct gk20a *get_gk20a(struct device *dev)
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{
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return gk20a_get_platform(dev)->g;
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}
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static inline struct gk20a *gk20a_from_dev(struct device *dev)
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{
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if (!dev)
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return NULL;
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return ((struct gk20a_platform *)dev_get_drvdata(dev))->g;
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}
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static inline bool gk20a_gpu_is_virtual(struct device *dev)
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{
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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return platform->virtual_dev;
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}
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static inline int support_gk20a_pmu(struct device *dev)
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{
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if (IS_ENABLED(CONFIG_GK20A_PMU)) {
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/* gPMU is not supported for vgpu */
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return !gk20a_gpu_is_virtual(dev);
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}
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return 0;
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}
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#endif
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