Open source GPL/LGPL release

drivers/gpu/nvgpu/os/linux/vgpu/fecs_trace_vgpu_linux.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <nvgpu/vgpu/tegra_vgpu.h>
+#include <nvgpu/vgpu/vgpu_ivm.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gr/fecs_trace.h>
+
+#include <linux/mm.h>
+
+#include "common/vgpu/gr/fecs_trace_vgpu.h"
+
+void vgpu_fecs_trace_data_update(struct gk20a *g)
+{
+	nvgpu_gr_fecs_trace_wake_up(g, 0);
+}
+
+int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size)
+{
+	struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
+
+	*buf = vcst->buf;
+	*size = vgpu_ivm_get_size(vcst->cookie);
+	return 0;
+}
+
+void vgpu_get_mmap_user_buffer_info(struct gk20a *g,
+				void **mmapaddr, size_t *mmapsize)
+{
+	struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
+
+	*mmapsize = vgpu_ivm_get_size(vcst->cookie);
+	*mmapaddr = (void *) (vgpu_ivm_get_ipa(vcst->cookie) >> PAGE_SHIFT);
+}

drivers/gpu/nvgpu/os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/platform_device.h>
+
+#include <linux/dma-mapping.h>
+
+#include <nvgpu/nvhost.h>
+#include <nvgpu/gk20a.h>
+
+#include "common/vgpu/clk_vgpu.h"
+#include "os/linux/platform_gk20a.h"
+#include "os/linux/os_linux.h"
+#include "os/linux/vgpu/vgpu_linux.h"
+#include "os/linux/vgpu/platform_vgpu_tegra.h"
+
+int gv11b_vgpu_probe(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gk20a_platform *platform = dev_get_drvdata(dev);
+	struct resource *r;
+	void __iomem *regs;
+	struct gk20a *g = platform->g;
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	int ret;
+#endif
+
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode");
+	if (!r) {
+		nvgpu_err(g, "failed to get usermode regs");
+		return -ENXIO;
+	}
+	regs = devm_ioremap_resource(dev, r);
+	if (IS_ERR(regs)) {
+		nvgpu_err(g, "failed to map usermode regs");
+		return PTR_ERR(regs);
+	}
+	g->usermode_regs = (uintptr_t)regs;
+
+	g->usermode_regs_bus_addr = r->start;
+
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	ret = nvgpu_get_nvhost_dev(g);
+	if (ret) {
+		g->usermode_regs = 0U;
+		return ret;
+	}
+
+	ret = nvgpu_nvhost_get_syncpt_aperture(g->nvhost,
+							&g->syncpt_unit_base,
+							&g->syncpt_unit_size);
+	if (ret) {
+		nvgpu_err(g, "Failed to get syncpt interface");
+		return -ENOSYS;
+	}
+	g->syncpt_size =
+		nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(g, 1);
+	nvgpu_info(g, "syncpt_unit_base %llx syncpt_unit_size %zx size %x\n",
+		g->syncpt_unit_base, g->syncpt_unit_size, g->syncpt_size);
+#endif
+	vgpu_init_clk_support(platform->g);
+
+	return 0;
+}
+
+struct gk20a_platform gv11b_vgpu_tegra_platform = {
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+	.has_syncpoints = true,
+#endif
+
+	/* power management configuration */
+	.can_railgate_init	= false,
+	.can_elpg_init          = false,
+	.enable_slcg            = false,
+	.enable_blcg            = false,
+	.enable_elcg            = false,
+	.enable_elpg            = false,
+	.enable_elpg_ms		= false,
+	.enable_aelpg           = false,
+	.can_slcg               = false,
+	.can_blcg               = false,
+	.can_elcg               = false,
+
+	.ch_wdt_init_limit_ms = 5000,
+
+	.probe = gv11b_vgpu_probe,
+
+	.clk_round_rate = vgpu_plat_clk_round_rate,
+	.get_clk_freqs = vgpu_plat_clk_get_freqs,
+
+	.platform_chip_id = TEGRA_194_VGPU,
+
+	/* frequency scaling configuration */
+	.devfreq_governor = "userspace",
+
+	.virtual_dev = true,
+
+	/* power management callbacks */
+	.suspend = vgpu_tegra_suspend,
+	.resume = vgpu_tegra_resume,
+
+	.unified_memory = true,
+	.dma_mask = DMA_BIT_MASK(36),
+};

drivers/gpu/nvgpu/os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef PLATFORM_GV11B_VGPU_LINUX_H
+#define PLATFORM_GV11B_VGPU_LINUX_H
+
+struct device;
+
+int gv11b_vgpu_probe(struct device *dev);
+
+#endif

drivers/gpu/nvgpu/os/linux/vgpu/platform_vgpu_tegra.c

@@ -0,0 +1,46 @@
+/*
+ * Tegra Virtualized GPU Platform Interface
+ *
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <nvgpu/gk20a.h>
+
+#include "os/linux/platform_gk20a.h"
+#include "common/vgpu/clk_vgpu.h"
+#include "vgpu_linux.h"
+
+long vgpu_plat_clk_round_rate(struct device *dev, unsigned long rate)
+{
+	/* server will handle frequency rounding */
+	return rate;
+}
+
+int vgpu_plat_clk_get_freqs(struct device *dev, unsigned long **freqs,
+			int *num_freqs)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a *g = platform->g;
+
+	return vgpu_clk_get_freqs(g, freqs, num_freqs);
+}
+
+int vgpu_plat_clk_cap_rate(struct device *dev, unsigned long rate)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a *g = platform->g;
+
+	return vgpu_clk_cap_rate(g, rate);
+}

drivers/gpu/nvgpu/os/linux/vgpu/platform_vgpu_tegra.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _VGPU_PLATFORM_H_
+#define _VGPU_PLATFORM_H_
+
+long vgpu_plat_clk_round_rate(struct device *dev, unsigned long rate);
+int vgpu_plat_clk_get_freqs(struct device *dev, unsigned long **freqs,
+			int *num_freqs);
+int vgpu_plat_clk_cap_rate(struct device *dev, unsigned long rate);
+#endif

drivers/gpu/nvgpu/os/linux/vgpu/sysfs_vgpu.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <nvgpu/vgpu/vgpu.h>
+
+#include "os/linux/platform_gk20a.h"
+#include "os/linux/os_linux.h"
+#include "common/vgpu/ecc_vgpu.h"
+#include "common/vgpu/ivc/comm_vgpu.h"
+
+static ssize_t vgpu_load_show(struct device *dev,
+			      struct device_attribute *attr,
+			      char *buf)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct tegra_vgpu_cmd_msg msg = {0};
+	struct tegra_vgpu_gpu_load_params *p = &msg.params.gpu_load;
+	int err;
+
+	msg.cmd = TEGRA_VGPU_CMD_GET_GPU_LOAD;
+	msg.handle = vgpu_get_handle(g);
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	if (err)
+		return err;
+
+	return snprintf(buf, NVGPU_CPU_PAGE_SIZE, "%u\n", p->load);
+}
+static DEVICE_ATTR(load, S_IRUGO, vgpu_load_show, NULL);
+
+static ssize_t vgpu_ecc_stat_show(struct device *dev,
+			      struct device_attribute *attr,
+			      char *buf)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct tegra_vgpu_cmd_msg msg = {0};
+	struct tegra_vgpu_ecc_counter_params *p = &msg.params.ecc_counter;
+	struct dev_ext_attribute *ext_attr = container_of(attr,
+			struct dev_ext_attribute, attr);
+	struct vgpu_ecc_stat *ecc_stat = ext_attr->var;
+	int err;
+
+	p->ecc_id = ecc_stat->ecc_id;
+
+	msg.cmd = TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE;
+	msg.handle = vgpu_get_handle(g);
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err ? err : msg.ret;
+	if (unlikely(err)) {
+		nvgpu_err(g, "ecc: cannot get ECC counter value: %d", err);
+		return err;
+	}
+
+	return snprintf(buf, NVGPU_CPU_PAGE_SIZE, "%u\n", p->value);
+}
+
+static int vgpu_create_ecc_sysfs(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+	struct vgpu_ecc_stat *stats;
+	struct dev_ext_attribute *attrs;
+	int err, i, count;
+
+	err = vgpu_ecc_get_info(g);
+	if (unlikely(err)) {
+		nvgpu_err(g, "ecc: cannot get ECC info: %d", err);
+		return err;
+	}
+
+	stats = priv->ecc_stats;
+	count = priv->ecc_stats_count;
+
+	attrs = nvgpu_kzalloc(g, count * sizeof(*attrs));
+	if (unlikely(!attrs)) {
+		nvgpu_err(g, "ecc: no memory");
+		vgpu_ecc_remove_info(g);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < count; i++) {
+		sysfs_attr_init(&attrs[i].attr.attr);
+		attrs[i].attr.attr.name = stats[i].name;
+		attrs[i].attr.attr.mode = VERIFY_OCTAL_PERMISSIONS(S_IRUGO);
+		attrs[i].attr.show = vgpu_ecc_stat_show;
+		attrs[i].attr.store = NULL;
+		attrs[i].var = &stats[i];
+
+		err = device_create_file(dev, &attrs[i].attr);
+		if (unlikely(err)) {
+			nvgpu_warn(g, "ecc: cannot create file \"%s\": %d",
+				   stats[i].name, err);
+		}
+	}
+
+	l->ecc_attrs = attrs;
+	return 0;
+}
+
+static void vgpu_remove_ecc_sysfs(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+	int i;
+
+	if (l->ecc_attrs) {
+		for (i = 0; i < priv->ecc_stats_count; i++)
+			device_remove_file(dev, &l->ecc_attrs[i].attr);
+
+		nvgpu_kfree(g, l->ecc_attrs);
+		l->ecc_attrs = NULL;
+	}
+
+	vgpu_ecc_remove_info(g);
+}
+
+void vgpu_create_sysfs(struct device *dev)
+{
+	if (device_create_file(dev, &dev_attr_load))
+		dev_err(dev, "Failed to create vgpu sysfs attributes!\n");
+
+	vgpu_create_ecc_sysfs(dev);
+}
+
+void vgpu_remove_sysfs(struct device *dev)
+{
+	device_remove_file(dev, &dev_attr_load);
+	vgpu_remove_ecc_sysfs(dev);
+}

drivers/gpu/nvgpu/os/linux/vgpu/vgpu_ivc.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018, NVIDIA Corporation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <nvgpu/types.h>
+#include <linux/tegra_gr_comm.h>
+
+#include "os/linux/os_linux.h"
+
+int vgpu_ivc_init(struct gk20a *g, u32 elems,
+		const size_t *queue_sizes, u32 queue_start, u32 num_queues)
+{
+	struct platform_device *pdev = to_platform_device(dev_from_gk20a(g));
+
+	return tegra_gr_comm_init(pdev, elems, queue_sizes, queue_start,
+				num_queues);
+}
+
+void vgpu_ivc_deinit(u32 queue_start, u32 num_queues)
+{
+	tegra_gr_comm_deinit(queue_start, num_queues);
+}
+
+void vgpu_ivc_release(void *handle)
+{
+	tegra_gr_comm_release(handle);
+}
+
+u32 vgpu_ivc_get_server_vmid(void)
+{
+	return tegra_gr_comm_get_server_vmid();
+}
+
+int vgpu_ivc_recv(u32 index, void **handle, void **data,
+				size_t *size, u32 *sender)
+{
+	return tegra_gr_comm_recv(index, handle, data, size, sender);
+}
+
+int vgpu_ivc_send(u32 peer, u32 index, void *data, size_t size)
+{
+	return tegra_gr_comm_send(peer, index, data, size);
+}
+
+int vgpu_ivc_sendrecv(u32 peer, u32 index, void **handle,
+				void **data, size_t *size)
+{
+	return tegra_gr_comm_sendrecv(peer, index, handle, data, size);
+}
+
+u32 vgpu_ivc_get_peer_self(void)
+{
+	return TEGRA_GR_COMM_ID_SELF;
+}
+
+void *vgpu_ivc_oob_get_ptr(u32 peer, u32 index, void **ptr,
+					size_t *size)
+{
+	return tegra_gr_comm_oob_get_ptr(peer, index, ptr, size);
+}
+
+void vgpu_ivc_oob_put_ptr(void *handle)
+{
+	tegra_gr_comm_oob_put_ptr(handle);
+}

drivers/gpu/nvgpu/os/linux/vgpu/vgpu_ivm.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018, NVIDIA Corporation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <nvgpu/vgpu/vgpu_ivm.h>
+
+#include <linux/tegra-ivc.h>
+
+#include "os/linux/os_linux.h"
+
+struct tegra_hv_ivm_cookie *vgpu_ivm_mempool_reserve(unsigned int id)
+{
+	return tegra_hv_mempool_reserve(id);
+}
+
+int vgpu_ivm_mempool_unreserve(struct tegra_hv_ivm_cookie *cookie)
+{
+	return tegra_hv_mempool_unreserve(cookie);
+}
+
+u64 vgpu_ivm_get_ipa(struct tegra_hv_ivm_cookie *cookie)
+{
+	return cookie->ipa;
+}
+
+u64 vgpu_ivm_get_size(struct tegra_hv_ivm_cookie *cookie)
+{
+	return cookie->size;
+}
+
+void *vgpu_ivm_mempool_map(struct tegra_hv_ivm_cookie *cookie)
+{
+	return ioremap_cache(vgpu_ivm_get_ipa(cookie),
+				vgpu_ivm_get_size(cookie));
+}
+
+void vgpu_ivm_mempool_unmap(struct tegra_hv_ivm_cookie *cookie,
+		void *addr)
+{
+	iounmap(addr);
+}

drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c

@@ -0,0 +1,555 @@
+/*
+ * Virtualized GPU for Linux
+ *
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_qos.h>
+#include <linux/platform_device.h>
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)
+#include <soc/tegra/chip-id.h>
+#else
+#include <soc/tegra/fuse.h>
+#endif
+#endif
+
+#include <nvgpu/kmem.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/errata.h>
+#include <nvgpu/debug.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/defaults.h>
+#include <nvgpu/ltc.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/tsg.h>
+#include <nvgpu/regops.h>
+#include <nvgpu/clk_arb.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/nvgpu_init.h>
+
+#include <nvgpu/vgpu/os_init_hal_vgpu.h>
+
+#include "vgpu_linux.h"
+#include "common/vgpu/gr/fecs_trace_vgpu.h"
+#include "common/vgpu/clk_vgpu.h"
+#include "common/vgpu/ivc/comm_vgpu.h"
+#include "common/vgpu/intr/intr_vgpu.h"
+#include "common/vgpu/init/init_vgpu.h"
+
+#include "os/linux/module.h"
+#include "os/linux/os_linux.h"
+#include "os/linux/ioctl.h"
+#include "os/linux/scale.h"
+#include "os/linux/driver_common.h"
+#include "os/linux/platform_gk20a.h"
+#include "os/linux/vgpu/platform_vgpu_tegra.h"
+#include "os/linux/dmabuf_priv.h"
+
+struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g)
+{
+	struct gk20a_platform *plat = gk20a_get_platform(dev_from_gk20a(g));
+
+	return (struct vgpu_priv_data *)plat->vgpu_priv;
+}
+
+static void vgpu_remove_support(struct gk20a *g)
+{
+	vgpu_remove_support_common(g);
+
+	/* free mappings to registers, etc*/
+
+	if (g->bar1) {
+		iounmap((void __iomem *)g->bar1);
+		g->bar1 = 0U;
+	}
+}
+
+static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform)
+{
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+
+	nvgpu_spinlock_init(&g->power_spinlock);
+
+	nvgpu_mutex_init(&g->power_lock);
+	nvgpu_mutex_init(&g->clk_arb_enable_lock);
+	nvgpu_mutex_init(&g->cg_pg_lock);
+	nvgpu_rwsem_init(&g->deterministic_busy);
+
+	nvgpu_mutex_init(&priv->vgpu_clk_get_freq_lock);
+
+	nvgpu_mutex_init(&l->ctrl_privs_lock);
+	nvgpu_init_list_node(&l->ctrl_privs);
+
+	g->regs_saved = g->regs;
+	g->bar1_saved = g->bar1;
+
+	nvgpu_atomic_set(&g->clk_arb_global_nr, 0);
+
+	g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
+	nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, platform->has_syncpoints);
+	g->ptimer_src_freq = platform->ptimer_src_freq;
+	nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init);
+	g->railgate_delay = platform->railgate_delay_init;
+
+	g->mm.disable_bigpage = NVGPU_CPU_PAGE_SIZE < SZ_64K;
+	nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY,
+			    platform->unified_memory);
+	nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES,
+			    platform->unify_address_spaces);
+}
+
+static int vgpu_init_support(struct platform_device *pdev)
+{
+	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	struct gk20a *g = get_gk20a(&pdev->dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	void __iomem *regs;
+	int err = 0;
+
+	if (!r) {
+		nvgpu_err(g, "failed to get gk20a bar1");
+		err = -ENXIO;
+		goto fail;
+	}
+
+	if (r->name && !strcmp(r->name, "/vgpu")) {
+		regs = devm_ioremap_resource(&pdev->dev, r);
+		if (IS_ERR(regs)) {
+			nvgpu_err(g, "failed to remap gk20a bar1");
+			err = PTR_ERR(regs);
+			goto fail;
+		}
+		g->bar1 = (uintptr_t)regs;
+		l->bar1_mem = r;
+	}
+
+	nvgpu_mutex_init(&g->dbg_sessions_lock);
+	nvgpu_mutex_init(&g->client_lock);
+#if defined(CONFIG_NVGPU_CYCLESTATS)
+	nvgpu_mutex_init(&g->cs_lock);
+#endif
+
+	nvgpu_init_list_node(&g->profiler_objects);
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+	g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K);
+	if (!g->dbg_regops_tmp_buf) {
+		nvgpu_err(g, "couldn't allocate regops tmp buf");
+		err = -ENOMEM;
+	}
+	g->dbg_regops_tmp_buf_ops =
+		SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]);
+#endif
+
+	g->remove_support = vgpu_remove_support;
+	return 0;
+
+ fail:
+	vgpu_remove_support(g);
+	return err;
+}
+
+int vgpu_pm_prepare_poweroff(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	int ret = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_mutex_acquire(&g->power_lock);
+
+	if (nvgpu_is_powered_off(g))
+		goto done;
+
+	if (g->ops.channel.suspend_all_serviceable_ch != NULL) {
+		ret = g->ops.channel.suspend_all_serviceable_ch(g);
+	}
+
+	if (ret != 0) {
+		goto done;
+	}
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF);
+
+ done:
+	nvgpu_mutex_release(&g->power_lock);
+
+	return ret;
+}
+
+int vgpu_pm_finalize_poweron(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_mutex_acquire(&g->power_lock);
+
+	if (nvgpu_is_powered_on(g))
+		goto done;
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERING_ON);
+
+	err = vgpu_finalize_poweron_common(g);
+	if (err)
+		goto done;
+
+	if (!l->dev_nodes_created) {
+		err = gk20a_user_nodes_init(dev);
+		if (err) {
+			goto done;
+		}
+
+		l->dev_nodes_created = true;
+	}
+
+	/* Initialize linux specific flags */
+	gk20a_init_linux_characteristics(g);
+
+	err = nvgpu_finalize_poweron_linux(l);
+	if (err)
+		goto done;
+
+	gk20a_sched_ctrl_init(g);
+
+	g->sw_ready = true;
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON);
+
+done:
+	nvgpu_mutex_release(&g->power_lock);
+	return err;
+}
+
+#ifdef CONFIG_GK20A_PM_QOS
+
+static int vgpu_qos_notify(struct notifier_block *nb,
+			  unsigned long n, void *data)
+{
+	struct gk20a_scale_profile *profile =
+			container_of(nb, struct gk20a_scale_profile,
+			qos_notify_block);
+	struct gk20a *g = get_gk20a(profile->dev);
+	u64 max_freq;
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	max_freq = (u64)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS) * 1000UL;
+	err = vgpu_plat_clk_cap_rate(profile->dev, max_freq);
+	if (err)
+		nvgpu_err(g, "%s failed, err=%d", __func__, err);
+
+	return NOTIFY_OK; /* need notify call further */
+}
+
+static int vgpu_pm_qos_init(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct gk20a_scale_profile *profile = g->scale_profile;
+
+	if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) {
+		if (!profile)
+			return -EINVAL;
+	} else {
+		profile = nvgpu_kzalloc(g, sizeof(*profile));
+		if (!profile)
+			return -ENOMEM;
+		g->scale_profile = profile;
+	}
+
+	profile->dev = dev;
+	profile->qos_notify_block.notifier_call = vgpu_qos_notify;
+	pm_qos_add_max_notifier(PM_QOS_GPU_FREQ_BOUNDS,
+				&profile->qos_notify_block);
+	return 0;
+}
+
+static void vgpu_pm_qos_remove(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+
+	pm_qos_remove_max_notifier(PM_QOS_GPU_FREQ_BOUNDS,
+				&g->scale_profile->qos_notify_block);
+	nvgpu_kfree(g, g->scale_profile);
+	g->scale_profile = NULL;
+}
+
+#endif
+
+static int vgpu_pm_init(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	if (nvgpu_platform_is_simulation(g))
+		return 0;
+
+	__pm_runtime_disable(dev, false);
+
+	if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
+		gk20a_scale_init(dev);
+
+#ifdef CONFIG_GK20A_PM_QOS
+	err = vgpu_pm_qos_init(dev);
+	if (err)
+		return err;
+#endif
+
+	return err;
+}
+
+int vgpu_probe(struct platform_device *pdev)
+{
+	struct nvgpu_os_linux *l;
+	struct gk20a *gk20a;
+	int err;
+	struct device *dev = &pdev->dev;
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct vgpu_priv_data *priv;
+
+	if (!platform) {
+		dev_err(dev, "no platform data\n");
+		return -ENODATA;
+	}
+
+	l = kzalloc(sizeof(*l), GFP_KERNEL);
+	if (!l) {
+		dev_err(dev, "couldn't allocate gk20a support");
+		return -ENOMEM;
+	}
+	gk20a = &l->g;
+	gk20a->log_mask = NVGPU_DEFAULT_DBG_MASK;
+
+	nvgpu_log_fn(gk20a, " ");
+
+	nvgpu_init_gk20a(gk20a);
+
+	nvgpu_kmem_init(gk20a);
+
+	err = nvgpu_init_errata_flags(gk20a);
+	if (err) {
+		kfree(gk20a);
+		return err;
+	}
+
+	err = nvgpu_init_enabled_flags(gk20a);
+	if (err) {
+		nvgpu_free_errata_flags(gk20a);
+		kfree(gk20a);
+		return err;
+	}
+
+	l->dev = dev;
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
+	if (tegra_platform_is_vdk())
+		nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
+#endif
+
+	gk20a->is_virtual = true;
+
+	priv = nvgpu_kzalloc(gk20a, sizeof(*priv));
+	if (!priv) {
+		kfree(gk20a);
+		return -ENOMEM;
+	}
+
+	platform->g = gk20a;
+	platform->vgpu_priv = priv;
+
+	err = vgpu_init_support(pdev);
+	if (err != 0) {
+		kfree(l);
+		return -ENOMEM;
+	}
+
+	vgpu_init_vars(gk20a, platform);
+
+	init_rwsem(&l->busy_lock);
+
+	nvgpu_spinlock_init(&gk20a->mc.enable_lock);
+
+	nvgpu_spinlock_init(&gk20a->mc.intr_lock);
+
+	gk20a->ch_wdt_init_limit_ms = platform->ch_wdt_init_limit_ms;
+
+	/* Initialize the platform interface. */
+	err = platform->probe(dev);
+	if (err) {
+		if (err == -EPROBE_DEFER)
+			nvgpu_info(gk20a, "platform probe failed");
+		else
+			nvgpu_err(gk20a, "platform probe failed");
+		return err;
+	}
+
+	if (platform->late_probe) {
+		err = platform->late_probe(dev);
+		if (err) {
+			nvgpu_err(gk20a, "late probe failed");
+			return err;
+		}
+	}
+
+	err = gk20a_power_node_init(dev);
+	if (err) {
+		nvgpu_err(gk20a, "power_node creation failed");
+		return err;
+	}
+
+	err = vgpu_comm_init(gk20a);
+	if (err) {
+		nvgpu_err(gk20a, "failed to init comm interface");
+		return -ENOSYS;
+	}
+
+	priv->virt_handle = vgpu_connect();
+	if (!priv->virt_handle) {
+		nvgpu_err(gk20a, "failed to connect to server node");
+		vgpu_comm_deinit();
+		return -ENOSYS;
+	}
+
+	err = vgpu_get_constants(gk20a);
+	if (err) {
+		vgpu_comm_deinit();
+		return err;
+	}
+
+	err = vgpu_pm_init(dev);
+	if (err) {
+		nvgpu_err(gk20a, "pm init failed");
+		return err;
+	}
+
+	err = nvgpu_thread_create(&priv->intr_handler, gk20a,
+			vgpu_intr_thread, "gk20a");
+	if (err) {
+		return err;
+	}
+
+	gk20a_debug_init(gk20a, "gpu.0");
+
+	/* Set DMA parameters to allow larger sgt lists */
+	dev->dma_parms = &l->dma_parms;
+	dma_set_max_seg_size(dev, UINT_MAX);
+
+	/*
+	 * A default of 16GB is the largest supported DMA size that is
+	 * acceptable to all currently supported Tegra SoCs.
+	 */
+	if (!platform->dma_mask)
+		platform->dma_mask = DMA_BIT_MASK(34);
+
+	dma_set_mask(dev, platform->dma_mask);
+	dma_set_coherent_mask(dev, platform->dma_mask);
+	dma_set_seg_boundary(dev, platform->dma_mask);
+
+	gk20a->poll_timeout_default = NVGPU_DEFAULT_POLL_TIMEOUT_MS;
+	gk20a->timeouts_disabled_by_user = false;
+	nvgpu_atomic_set(&gk20a->timeouts_disabled_refcount, 0);
+	gk20a->tsg_dbg_timeslice_max_us = NVGPU_TSG_DBG_TIMESLICE_MAX_US_DEFAULT;
+	vgpu_create_sysfs(dev);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
+	nvgpu_log_info(gk20a, "total ram pages : %lu", totalram_pages());
+#else
+	nvgpu_log_info(gk20a, "total ram pages : %lu", totalram_pages);
+#endif
+	gk20a->max_comptag_mem = totalram_size_in_mb;
+
+	nvgpu_mutex_init(&l->dmabuf_priv_list_lock);
+	nvgpu_init_list_node(&l->dmabuf_priv_list);
+
+	nvgpu_ref_init(&gk20a->refcount);
+
+	return 0;
+}
+
+int vgpu_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct gk20a *g = get_gk20a(dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+
+	nvgpu_log_fn(g, " ");
+
+	gk20a_dma_buf_priv_list_clear(l);
+	nvgpu_mutex_destroy(&l->dmabuf_priv_list_lock);
+
+#ifdef CONFIG_GK20A_PM_QOS
+	vgpu_pm_qos_remove(dev);
+#endif
+	if (g->remove_support)
+		g->remove_support(g);
+
+	vgpu_comm_deinit();
+	gk20a_sched_ctrl_cleanup(g);
+	gk20a_user_nodes_deinit(dev);
+	vgpu_remove_sysfs(dev);
+	gk20a_get_platform(dev)->g = NULL;
+	nvgpu_put(g);
+
+	return 0;
+}
+
+int vgpu_tegra_suspend(struct device *dev)
+{
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct gk20a *g = get_gk20a(dev);
+	int err = 0;
+
+	msg.cmd = TEGRA_VGPU_CMD_SUSPEND;
+	msg.handle = vgpu_get_handle(g);
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err ? err : msg.ret;
+	if (err)
+		nvgpu_err(g, "vGPU suspend failed\n");
+
+	return err;
+}
+
+int vgpu_tegra_resume(struct device *dev)
+{
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct gk20a *g = get_gk20a(dev);
+	int err = 0;
+
+	msg.cmd = TEGRA_VGPU_CMD_RESUME;
+	msg.handle = vgpu_get_handle(g);
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err ? err : msg.ret;
+	if (err)
+		nvgpu_err(g, "vGPU resume failed\n");
+
+	return err;
+}
+
+int vgpu_init_hal_os(struct gk20a *g)
+{
+	return 0;
+}

drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.h

@@ -0,0 +1,68 @@
+/*
+ * Virtualized GPU Linux Interfaces
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __VGPU_LINUX_H__
+#define __VGPU_LINUX_H__
+
+struct device;
+struct platform_device;
+
+#ifdef CONFIG_NVGPU_GR_VIRTUALIZATION
+
+#include <nvgpu/vgpu/vgpu.h>
+
+int vgpu_pm_prepare_poweroff(struct device *dev);
+int vgpu_pm_finalize_poweron(struct device *dev);
+int vgpu_probe(struct platform_device *dev);
+int vgpu_remove(struct platform_device *dev);
+
+void vgpu_create_sysfs(struct device *dev);
+void vgpu_remove_sysfs(struct device *dev);
+
+int vgpu_tegra_suspend(struct device *dev);
+int vgpu_tegra_resume(struct device *dev);
+#else
+/* define placeholders for functions used outside of vgpu */
+
+static inline int vgpu_pm_prepare_poweroff(struct device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_pm_finalize_poweron(struct device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_probe(struct platform_device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_remove(struct platform_device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_tegra_suspend(struct device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_tegra_resume(struct device *dev)
+{
+	return -ENOSYS;
+}
+#endif
+
+#endif