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gpu: nvgpu: Fold T19x code back to main code paths

Browse Source 
Lots of code paths were split to T19x specific code paths and structs
due to split repository. Now that repositories are merged, fold all of
them back to main code paths and structs and remove the T19x specific
Kconfig flag.

Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640606
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-01-17 12:39:13 -08:00
committed by mobile promotions
parent 193a2ed38c
commit f3f14cdff5
77 changed files with 439 additions and 1160 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/linux/io_t19x.c → drivers/gpu/nvgpu/common/linux/io_usermode.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -19,10 +19,10 @@
#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v)
void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
void __iomem *reg = l->t19x.usermode_regs + (r - usermode_cfg0_r());
void __iomem *reg = l->usermode_regs + (r - usermode_cfg0_r());
writel_relaxed(v, reg);
gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v);

11
drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2017, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -35,9 +35,6 @@
#include "ioctl_ctrl.h"
#include "ioctl_dbg.h"
#include "ioctl_as.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include "common/linux/ioctl_ctrl_t19x.h"
#endif
#include "ioctl_tsg.h"
#include "ioctl_channel.h"
#include "gk20a/gk20a.h"
@@ -173,6 +170,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
NVGPU_ECC_ENABLED_TEX},
{NVGPU_GPU_FLAGS_ECC_ENABLED_LTC,
NVGPU_ECC_ENABLED_LTC},
{NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS,
NVGPU_SUPPORT_TSG_SUBCONTEXTS},
};
static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
@@ -240,9 +239,7 @@ gk20a_ctrl_ioctl_gpu_characteristics(
gpu.gpc_mask = (1 << g->gr.gpc_count)-1;
gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g);
#ifdef CONFIG_TEGRA_19x_GPU
gpu.flags |= nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(g);
#endif
gpu.arch = g->params.gpu_arch;
gpu.impl = g->params.gpu_impl;
gpu.rev = g->params.gpu_rev;

33
drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c
View File

@@ -1,33 +0,0 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <uapi/linux/nvgpu.h>
#include <nvgpu/types.h>
#include <nvgpu/enabled.h>
#include <nvgpu/enabled_t19x.h>
#include "ioctl_ctrl_t19x.h"
#include "common/linux/os_linux.h"
#include "gk20a/gk20a.h"
u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g)
{
u64 ioctl_flags = 0;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS))
ioctl_flags |= NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS;
return ioctl_flags;
}

23
drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _NVGPU_IOCTL_CTRL_T19X
#define _NVGPU_IOCTL_CTRL_T19X
#include <nvgpu/types.h>
struct gk20a;
u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g);
#endif

83
drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -27,13 +27,11 @@
#include "gk20a/gk20a.h"
#include "gk20a/tsg_gk20a.h"
#include "gv11b/fifo_gv11b.h"
#include "platform_gk20a.h"
#include "ioctl_tsg.h"
#include "ioctl_channel.h"
#include "os_linux.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include "common/linux/ioctl_tsg_t19x.h"
#endif
struct tsg_private {
struct gk20a *g;
@@ -55,6 +53,72 @@ static int gk20a_tsg_bind_channel_fd(struct tsg_gk20a *tsg, int ch_fd)
return err;
}
static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
struct channel_gk20a *ch;
struct gr_gk20a *gr = &g->gr;
int err = 0;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
nvgpu_mutex_acquire(&sched->control_lock);
if (sched->control_locked) {
err = -EPERM;
goto mutex_release;
}
err = gk20a_busy(g);
if (err) {
nvgpu_err(g, "failed to power on gpu");
goto mutex_release;
}
ch = gk20a_get_channel_from_file(arg->channel_fd);
if (!ch) {
err = -EINVAL;
goto idle;
}
if (arg->tpc_pg_enabled && (!tsg->tpc_num_initialized)) {
if ((arg->num_active_tpcs > gr->max_tpc_count) ||
!(arg->num_active_tpcs)) {
nvgpu_err(g, "Invalid num of active TPCs");
err = -EINVAL;
goto ch_put;
}
tsg->tpc_num_initialized = true;
tsg->num_active_tpcs = arg->num_active_tpcs;
tsg->tpc_pg_enabled = true;
} else {
tsg->tpc_pg_enabled = false; nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled");
}
if (arg->subcontext_id < g->fifo.max_subctx_count) {
ch->subctx_id = arg->subcontext_id;
} else {
err = -EINVAL;
goto ch_put;
}
nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d",
ch->chid, ch->subctx_id);
/* Use runqueue selector 1 for all ASYNC ids */
if (ch->subctx_id > CHANNEL_INFO_VEID0)
ch->runqueue_sel = 1;
err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch);
ch_put:
gk20a_channel_put(ch);
idle:
gk20a_idle(g);
mutex_release:
nvgpu_mutex_release(&sched->control_lock);
return err;
}
static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg,
unsigned int event_id,
struct gk20a_event_id_data **event_id_data)
@@ -478,6 +542,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
break;
}
case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX:
{
err = gk20a_tsg_ioctl_bind_channel_ex(g, tsg,
(struct nvgpu_tsg_bind_channel_ex_args *)buf);
break;
}
case NVGPU_TSG_IOCTL_UNBIND_CHANNEL:
/* We do not support explicitly unbinding channel from TSG.
* Channel will be unbounded from TSG when it is closed.
@@ -550,13 +621,9 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
}
default:
#ifdef CONFIG_TEGRA_19x_GPU
err = t19x_tsg_ioctl_handler(g, tsg, cmd, buf);
#else
nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x",
cmd);
err = -ENOTTY;
#endif
break;
}

115
drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c
View File

@@ -1,115 +0,0 @@
/*
* GV11B TSG IOCTL Handler
*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/types.h>
#include <uapi/linux/nvgpu.h>
#include "gk20a/gk20a.h"
#include "gv11b/fifo_gv11b.h"
#include "gv11b/subctx_gv11b.h"
#include "ioctl_tsg_t19x.h"
#include "common/linux/os_linux.h"
static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g,
struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
struct channel_gk20a *ch;
struct gr_gk20a *gr = &g->gr;
int err = 0;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
nvgpu_mutex_acquire(&sched->control_lock);
if (sched->control_locked) {
err = -EPERM;
goto mutex_release;
}
err = gk20a_busy(g);
if (err) {
nvgpu_err(g, "failed to power on gpu");
goto mutex_release;
}
ch = gk20a_get_channel_from_file(arg->channel_fd);
if (!ch) {
err = -EINVAL;
goto idle;
}
if (arg->tpc_pg_enabled && (!tsg->t19x.tpc_num_initialized)) {
if ((arg->num_active_tpcs > gr->max_tpc_count) ||
!(arg->num_active_tpcs)) {
nvgpu_err(g, "Invalid num of active TPCs");
err = -EINVAL;
goto ch_put;
}
tsg->t19x.tpc_num_initialized = true;
tsg->t19x.num_active_tpcs = arg->num_active_tpcs;
tsg->t19x.tpc_pg_enabled = true;
} else {
tsg->t19x.tpc_pg_enabled = false;
nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled");
}
if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) {
ch->t19x.subctx_id = arg->subcontext_id;
} else {
err = -EINVAL;
goto ch_put;
}
nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d",
ch->chid, ch->t19x.subctx_id);
/* Use runqueue selector 1 for all ASYNC ids */
if (ch->t19x.subctx_id > CHANNEL_INFO_VEID0)
ch->t19x.runqueue_sel = 1;
err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch);
ch_put:
gk20a_channel_put(ch);
idle:
gk20a_idle(g);
mutex_release:
nvgpu_mutex_release(&sched->control_lock);
return err;
}
int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg,
unsigned int cmd, u8 *buf)
{
int err = 0;
nvgpu_log(g, gpu_dbg_fn, "t19x_tsg_ioctl_handler");
switch (cmd) {
case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX:
{
err = gv11b_tsg_ioctl_bind_channel_ex(g, tsg,
(struct nvgpu_tsg_bind_channel_ex_args *)buf);
break;
}
default:
nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x",
cmd);
err = -ENOTTY;
break;
}
return err;
}

26
drivers/gpu/nvgpu/common/linux/module.c
View File

@@ -46,13 +46,11 @@
#include "scale.h"
#include "pci.h"
#include "module.h"
#include "module_usermode.h"
#include "intr.h"
#include "cde.h"
#include "ioctl.h"
#include "sim.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include "nvgpu_gpuid_t19x.h"
#endif
#include "os_linux.h"
#include "cde_gm20b.h"
@@ -175,9 +173,7 @@ static int gk20a_restore_registers(struct gk20a *g)
l->regs = l->regs_saved;
l->bar1 = l->bar1_saved;
#ifdef CONFIG_TEGRA_19x_GPU
t19x_restore_registers(g);
#endif
nvgpu_restore_usermode_registers(g);
return 0;
}
@@ -313,9 +309,7 @@ static int gk20a_lockout_registers(struct gk20a *g)
l->regs = NULL;
l->bar1 = NULL;
#ifdef CONFIG_TEGRA_19x_GPU
t19x_lockout_registers(g);
#endif
nvgpu_lockout_usermode_registers(g);
return 0;
}
@@ -384,14 +378,12 @@ static struct of_device_id tegra_gk20a_of_match[] = {
.data = &gm20b_tegra_platform },
{ .compatible = "nvidia,tegra186-gp10b",
.data = &gp10b_tegra_platform },
#ifdef CONFIG_TEGRA_19x_GPU
{ .compatible = TEGRA_19x_GPU_COMPAT_TEGRA,
.data = &t19x_gpu_tegra_platform },
{ .compatible = "nvidia,gv11b",
.data = &gv11b_tegra_platform },
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
{ .compatible = "nvidia,gv11b-vgpu",
.data = &gv11b_vgpu_tegra_platform},
#endif
#endif
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
{ .compatible = "nvidia,tegra124-gk20a-vgpu",
.data = &vgpu_tegra_platform },
@@ -669,9 +661,7 @@ void gk20a_remove_support(struct gk20a *g)
l->bar1 = NULL;
}
#ifdef CONFIG_TEGRA_19x_GPU
t19x_remove_support(g);
#endif
nvgpu_remove_usermode_support(g);
nvgpu_free_enabled_flags(g);
}
@@ -721,9 +711,7 @@ static int gk20a_init_support(struct platform_device *dev)
goto fail;
}
#ifdef CONFIG_TEGRA_19x_GPU
t19x_init_support(g);
#endif
nvgpu_init_usermode_support(g);
return 0;

6
drivers/gpu/nvgpu/common/linux/module.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -13,10 +13,6 @@
#ifndef __NVGPU_COMMON_LINUX_MODULE_H__
#define __NVGPU_COMMON_LINUX_MODULE_H__
#ifdef CONFIG_TEGRA_19x_GPU
#include <nvgpu/linux/module_t19x.h>
#endif
struct gk20a;
struct device;
struct nvgpu_os_linux;

22
drivers/gpu/nvgpu/common/linux/module_t19x.c → drivers/gpu/nvgpu/common/linux/module_usermode.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -27,36 +27,36 @@
* after the GPU has been turned off. On older chips these reads and writes can
* also lock the entire CPU up.
*/
void t19x_lockout_registers(struct gk20a *g)
void nvgpu_lockout_usermode_registers(struct gk20a *g)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
l->t19x.usermode_regs = NULL;
l->usermode_regs = NULL;
}
/*
* Undoes t19x_lockout_registers().
*/
void t19x_restore_registers(struct gk20a *g)
void nvgpu_restore_usermode_registers(struct gk20a *g)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
l->t19x.usermode_regs = l->t19x.usermode_regs_saved;
l->usermode_regs = l->usermode_regs_saved;
}
void t19x_remove_support(struct gk20a *g)
void nvgpu_remove_usermode_support(struct gk20a *g)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
if (l->t19x.usermode_regs) {
l->t19x.usermode_regs = NULL;
if (l->usermode_regs) {
l->usermode_regs = NULL;
}
}
void t19x_init_support(struct gk20a *g)
void nvgpu_init_usermode_support(struct gk20a *g)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
l->t19x.usermode_regs = l->regs + usermode_cfg0_r();
l->t19x.usermode_regs_saved = l->t19x.usermode_regs;
l->usermode_regs = l->regs + usermode_cfg0_r();
l->usermode_regs_saved = l->usermode_regs;
}

26
drivers/gpu/nvgpu/common/linux/nvhost_t19x.c → drivers/gpu/nvgpu/common/linux/module_usermode.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -14,22 +14,14 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/nvhost.h>
#include <linux/nvhost_t194.h>
#ifndef __NVGPU_MODULE_T19X_H__
#define __NVGPU_MODULE_T19X_H__
#include <nvgpu/nvhost_t19x.h>
struct gk20a;
#include "common/linux/nvhost_priv.h"
void nvgpu_init_usermode_support(struct gk20a *g);
void nvgpu_remove_usermode_support(struct gk20a *g);
void nvgpu_lockout_usermode_registers(struct gk20a *g);
void nvgpu_restore_usermode_registers(struct gk20a *g);
int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
struct nvgpu_nvhost_dev *nvhost_dev,
u64 *base, size_t *size)
{
return nvhost_syncpt_unit_interface_get_aperture(
nvhost_dev->host1x_pdev, (phys_addr_t *)base, size);
}
u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
{
return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id);
}
#endif

18
drivers/gpu/nvgpu/common/linux/nvhost.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -15,6 +15,7 @@
*/
#include <linux/nvhost.h>
#include <linux/nvhost_t194.h>
#include <linux/nvhost_ioctl.h>
#include <linux/of_platform.h>
@@ -210,3 +211,18 @@ struct sync_fence *nvgpu_nvhost_sync_create_fence(
return nvhost_sync_create_fence(nvhost_dev->host1x_pdev, &pt, 1, name);
}
#endif /* CONFIG_SYNC */
#ifdef CONFIG_TEGRA_T19X_GRHOST
int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
struct nvgpu_nvhost_dev *nvhost_dev,
u64 *base, size_t *size)
{
return nvhost_syncpt_unit_interface_get_aperture(
nvhost_dev->host1x_pdev, (phys_addr_t *)base, size);
}
u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
{
return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id);
}
#endif

10
drivers/gpu/nvgpu/common/linux/os_linux.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -20,9 +20,6 @@
#include <linux/cdev.h>
#include <linux/iommu.h>
#ifdef CONFIG_TEGRA_19x_GPU
#include <nvgpu/linux/os_linux_t19x.h>
#endif
#include "gk20a/gk20a.h"
#include "cde.h"
#include "sched.h"
@@ -114,9 +111,8 @@ struct nvgpu_os_linux {
void __iomem *bar1;
void __iomem *bar1_saved;
#ifdef CONFIG_TEGRA_19x_GPU
struct nvgpu_os_linux_t19x t19x;
#endif
void __iomem *usermode_regs;
void __iomem *usermode_regs_saved;
struct nvgpu_os_linux_ops ops;

10
drivers/gpu/nvgpu/common/linux/pci.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -34,9 +34,7 @@
#include "platform_gk20a.h"
#include "pci.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include <nvgpu/linux/pci_t19x.h>
#endif
#include "pci_usermode.h"
#include "os_linux.h"
#include "driver_common.h"
@@ -453,9 +451,7 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev)
goto fail;
}
#ifdef CONFIG_TEGRA_19x_GPU
t19x_nvgpu_pci_init_support(l);
#endif
nvgpu_pci_init_usermode_support(l);
return 0;

8
drivers/gpu/nvgpu/common/linux/pci_t19x.c → drivers/gpu/nvgpu/common/linux/pci_usermode.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -17,8 +17,8 @@
#include "common/linux/os_linux.h"
void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l)
void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l)
{
l->t19x.usermode_regs = l->regs + usermode_cfg0_r();
l->t19x.usermode_regs_saved = l->t19x.usermode_regs;
l->usermode_regs = l->regs + usermode_cfg0_r();
l->usermode_regs_saved = l->usermode_regs;
}

16
drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h → drivers/gpu/nvgpu/common/linux/pci_usermode.h
View File

@@ -1,7 +1,5 @@
/*
* GV11B TSG IOCTL handler
*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -11,11 +9,15 @@
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __NVGPU_PCI_USERMODE_H__
#define __NVGPU_PCI_USERMODE_H__
#ifndef _NVGPU_IOCTL_TSG_T19X
#define _NVGPU_IOCTL_TSG_T19X
struct nvgpu_os_linux;
void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l);
int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg,
unsigned int cmd, u8 *arg);
#endif

3
drivers/gpu/nvgpu/common/linux/platform_gk20a.h
View File

@@ -1,7 +1,7 @@
/*
* GK20A Platform (SoC) Interface
*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -250,6 +250,7 @@ static inline struct gk20a_platform *gk20a_get_platform(
#ifdef CONFIG_TEGRA_GK20A
extern struct gk20a_platform gm20b_tegra_platform;
extern struct gk20a_platform gp10b_tegra_platform;
extern struct gk20a_platform gv11b_tegra_platform;
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
extern struct gk20a_platform vgpu_tegra_platform;
extern struct gk20a_platform gv11b_vgpu_tegra_platform;

110
drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
View File

@@ -26,7 +26,6 @@
#include <linux/platform/tegra/emc_bwmgr.h>
#include <nvgpu/nvhost.h>
#include <nvgpu/nvhost_t19x.h>
#include <uapi/linux/nvgpu.h>
@@ -44,7 +43,6 @@
#include "os_linux.h"
#include "platform_gk20a_tegra.h"
#include "gv11b/gr_gv11b.h"
#include "nvgpu_gpuid_t19x.h"
static void gr_gv11b_remove_sysfs(struct device *dev);
@@ -203,7 +201,7 @@ static int gv11b_tegra_suspend(struct device *dev)
return 0;
}
struct gk20a_platform t19x_gpu_tegra_platform = {
struct gk20a_platform gv11b_tegra_platform = {
.has_syncpoints = true,
/* no cde. use sysmem compression */
@@ -297,7 +295,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
initialized multiple times but we only need to create the ECC
stats once. Therefore, add the following check to avoid
creating duplicate stat sysfs nodes. */
if (g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters != NULL)
if (g->ecc.gr.sm_l1_tag_corrected_err_count.counters != NULL)
return;
gr_gp10b_create_sysfs(g);
@@ -305,61 +303,61 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_l1_tag_ecc_corrected_err_count",
&g->ecc.gr.t19x.sm_l1_tag_corrected_err_count,
&g->ecc.gr.sm_l1_tag_corrected_err_count,
&dev_attr_sm_l1_tag_ecc_corrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_l1_tag_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count,
&g->ecc.gr.sm_l1_tag_uncorrected_err_count,
&dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_cbu_ecc_corrected_err_count",
&g->ecc.gr.t19x.sm_cbu_corrected_err_count,
&g->ecc.gr.sm_cbu_corrected_err_count,
&dev_attr_sm_cbu_ecc_corrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_cbu_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.sm_cbu_uncorrected_err_count,
&g->ecc.gr.sm_cbu_uncorrected_err_count,
&dev_attr_sm_cbu_ecc_uncorrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_l1_data_ecc_corrected_err_count",
&g->ecc.gr.t19x.sm_l1_data_corrected_err_count,
&g->ecc.gr.sm_l1_data_corrected_err_count,
&dev_attr_sm_l1_data_ecc_corrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_l1_data_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count,
&g->ecc.gr.sm_l1_data_uncorrected_err_count,
&dev_attr_sm_l1_data_ecc_uncorrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_icache_ecc_corrected_err_count",
&g->ecc.gr.t19x.sm_icache_corrected_err_count,
&g->ecc.gr.sm_icache_corrected_err_count,
&dev_attr_sm_icache_ecc_corrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"sm_icache_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.sm_icache_uncorrected_err_count,
&g->ecc.gr.sm_icache_uncorrected_err_count,
&dev_attr_sm_icache_ecc_uncorrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"gcc_l15_ecc_corrected_err_count",
&g->ecc.gr.t19x.gcc_l15_corrected_err_count,
&g->ecc.gr.gcc_l15_corrected_err_count,
&dev_attr_gcc_l15_ecc_corrected_err_count_array);
error |= gr_gp10b_ecc_stat_create(dev,
0,
"gcc_l15_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.gcc_l15_uncorrected_err_count,
&g->ecc.gr.gcc_l15_uncorrected_err_count,
&dev_attr_gcc_l15_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -368,7 +366,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"ltc",
NULL,
"l2_cache_uncorrected_err_count",
&g->ecc.ltc.t19x.l2_cache_uncorrected_err_count,
&g->ecc.ltc.l2_cache_uncorrected_err_count,
&dev_attr_l2_cache_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -377,7 +375,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"ltc",
NULL,
"l2_cache_corrected_err_count",
&g->ecc.ltc.t19x.l2_cache_corrected_err_count,
&g->ecc.ltc.l2_cache_corrected_err_count,
&dev_attr_l2_cache_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -386,7 +384,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"gpc",
NULL,
"fecs_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.fecs_uncorrected_err_count,
&g->ecc.gr.fecs_uncorrected_err_count,
&dev_attr_fecs_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -395,7 +393,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"gpc",
NULL,
"fecs_ecc_corrected_err_count",
&g->ecc.gr.t19x.fecs_corrected_err_count,
&g->ecc.gr.fecs_corrected_err_count,
&dev_attr_fecs_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -404,7 +402,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"gpc",
NULL,
"gpccs_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.gpccs_uncorrected_err_count,
&g->ecc.gr.gpccs_uncorrected_err_count,
&dev_attr_gpccs_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -413,7 +411,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"gpc",
NULL,
"gpccs_ecc_corrected_err_count",
&g->ecc.gr.t19x.gpccs_corrected_err_count,
&g->ecc.gr.gpccs_corrected_err_count,
&dev_attr_gpccs_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -422,7 +420,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"gpc",
NULL,
"mmu_l1tlb_ecc_uncorrected_err_count",
&g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count,
&g->ecc.gr.mmu_l1tlb_uncorrected_err_count,
&dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -431,7 +429,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"gpc",
NULL,
"mmu_l1tlb_ecc_corrected_err_count",
&g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count,
&g->ecc.gr.mmu_l1tlb_corrected_err_count,
&dev_attr_mmu_l1tlb_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -440,7 +438,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"mmu_l2tlb_ecc_uncorrected_err_count",
&g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count,
&g->ecc.fb.mmu_l2tlb_uncorrected_err_count,
&dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -449,7 +447,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"mmu_l2tlb_ecc_corrected_err_count",
&g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count,
&g->ecc.fb.mmu_l2tlb_corrected_err_count,
&dev_attr_mmu_l2tlb_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -458,7 +456,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"mmu_hubtlb_ecc_uncorrected_err_count",
&g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count,
&g->ecc.fb.mmu_hubtlb_uncorrected_err_count,
&dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -467,7 +465,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"mmu_hubtlb_ecc_corrected_err_count",
&g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count,
&g->ecc.fb.mmu_hubtlb_corrected_err_count,
&dev_attr_mmu_hubtlb_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -476,7 +474,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"mmu_fillunit_ecc_uncorrected_err_count",
&g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count,
&g->ecc.fb.mmu_fillunit_uncorrected_err_count,
&dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -485,7 +483,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"mmu_fillunit_ecc_corrected_err_count",
&g->ecc.eng.t19x.mmu_fillunit_corrected_err_count,
&g->ecc.fb.mmu_fillunit_corrected_err_count,
&dev_attr_mmu_fillunit_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -494,7 +492,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"pmu_ecc_uncorrected_err_count",
&g->ecc.eng.t19x.pmu_uncorrected_err_count,
&g->ecc.pmu.pmu_uncorrected_err_count,
&dev_attr_pmu_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
@@ -503,7 +501,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g)
"eng",
NULL,
"pmu_ecc_corrected_err_count",
&g->ecc.eng.t19x.pmu_corrected_err_count,
&g->ecc.pmu.pmu_corrected_err_count,
&dev_attr_pmu_ecc_corrected_err_count_array);
@@ -517,131 +515,131 @@ static void gr_gv11b_remove_sysfs(struct device *dev)
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_l1_tag_corrected_err_count,
&g->ecc.gr.sm_l1_tag_corrected_err_count,
dev_attr_sm_l1_tag_ecc_corrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count,
&g->ecc.gr.sm_l1_tag_uncorrected_err_count,
dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_cbu_corrected_err_count,
&g->ecc.gr.sm_cbu_corrected_err_count,
dev_attr_sm_cbu_ecc_corrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_cbu_uncorrected_err_count,
&g->ecc.gr.sm_cbu_uncorrected_err_count,
dev_attr_sm_cbu_ecc_uncorrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_l1_data_corrected_err_count,
&g->ecc.gr.sm_l1_data_corrected_err_count,
dev_attr_sm_l1_data_ecc_corrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count,
&g->ecc.gr.sm_l1_data_uncorrected_err_count,
dev_attr_sm_l1_data_ecc_uncorrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_icache_corrected_err_count,
&g->ecc.gr.sm_icache_corrected_err_count,
dev_attr_sm_icache_ecc_corrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.sm_icache_uncorrected_err_count,
&g->ecc.gr.sm_icache_uncorrected_err_count,
dev_attr_sm_icache_ecc_uncorrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.gcc_l15_corrected_err_count,
&g->ecc.gr.gcc_l15_corrected_err_count,
dev_attr_gcc_l15_ecc_corrected_err_count_array);
gr_gp10b_ecc_stat_remove(dev,
0,
&g->ecc.gr.t19x.gcc_l15_uncorrected_err_count,
&g->ecc.gr.gcc_l15_uncorrected_err_count,
dev_attr_gcc_l15_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
g->ltc_count,
&g->ecc.ltc.t19x.l2_cache_uncorrected_err_count,
&g->ecc.ltc.l2_cache_uncorrected_err_count,
dev_attr_l2_cache_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
g->ltc_count,
&g->ecc.ltc.t19x.l2_cache_corrected_err_count,
&g->ecc.ltc.l2_cache_corrected_err_count,
dev_attr_l2_cache_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.gr.t19x.fecs_uncorrected_err_count,
&g->ecc.gr.fecs_uncorrected_err_count,
dev_attr_fecs_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.gr.t19x.fecs_corrected_err_count,
&g->ecc.gr.fecs_corrected_err_count,
dev_attr_fecs_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
g->gr.gpc_count,
&g->ecc.gr.t19x.gpccs_uncorrected_err_count,
&g->ecc.gr.gpccs_uncorrected_err_count,
dev_attr_gpccs_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
g->gr.gpc_count,
&g->ecc.gr.t19x.gpccs_corrected_err_count,
&g->ecc.gr.gpccs_corrected_err_count,
dev_attr_gpccs_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
g->gr.gpc_count,
&g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count,
&g->ecc.gr.mmu_l1tlb_uncorrected_err_count,
dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
g->gr.gpc_count,
&g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count,
&g->ecc.gr.mmu_l1tlb_corrected_err_count,
dev_attr_mmu_l1tlb_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count,
&g->ecc.fb.mmu_l2tlb_uncorrected_err_count,
dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count,
&g->ecc.fb.mmu_l2tlb_corrected_err_count,
dev_attr_mmu_l2tlb_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count,
&g->ecc.fb.mmu_hubtlb_uncorrected_err_count,
dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count,
&g->ecc.fb.mmu_hubtlb_corrected_err_count,
dev_attr_mmu_hubtlb_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count,
&g->ecc.fb.mmu_fillunit_uncorrected_err_count,
dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_fillunit_corrected_err_count,
&g->ecc.fb.mmu_fillunit_corrected_err_count,
dev_attr_mmu_fillunit_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.pmu_uncorrected_err_count,
&g->ecc.pmu.pmu_uncorrected_err_count,
dev_attr_pmu_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.pmu_corrected_err_count,
&g->ecc.pmu.pmu_corrected_err_count,
dev_attr_pmu_ecc_corrected_err_count_array);
}

2
drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c
View File

@@ -169,10 +169,8 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
p->flags = TEGRA_VGPU_MAP_CACHEABLE;
if (flags & NVGPU_VM_MAP_IO_COHERENT)
p->flags |= TEGRA_VGPU_MAP_IO_COHERENT;
#ifdef CONFIG_TEGRA_19x_GPU
if (flags & NVGPU_VM_MAP_L3_ALLOC)
p->flags |= TEGRA_VGPU_MAP_L3_ALLOC;
#endif
p->prot = prot;
p->ctag_offset = ctag_offset;
p->clear_ctags = clear_ctags;

7
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -20,7 +20,6 @@
#include "common/linux/os_linux.h"
#include <nvgpu/nvhost.h>
#include <nvgpu/nvhost_t19x.h>
#include <linux/platform_device.h>
@@ -44,12 +43,12 @@ static int gv11b_vgpu_probe(struct device *dev)
dev_err(dev, "failed to map usermode regs\n");
return PTR_ERR(regs);
}
l->t19x.usermode_regs = regs;
l->usermode_regs = regs;
#ifdef CONFIG_TEGRA_GK20A_NVHOST
ret = nvgpu_get_nvhost_dev(g);
if (ret) {
l->t19x.usermode_regs = NULL;
l->usermode_regs = NULL;
return ret;
}

6
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -18,7 +18,7 @@
#include "common/linux/vgpu/vgpu.h"
#include "gv11b/fifo_gv11b.h"
#include <nvgpu/nvhost_t19x.h>
#include <nvgpu/nvhost.h>
#include <linux/tegra_vgpu.h>
@@ -99,7 +99,7 @@ int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
struct fifo_gk20a *f = &g->fifo;
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
f->t19x.max_subctx_count = priv->constants.max_subctx_count;
f->max_subctx_count = priv->constants.max_subctx_count;
return 0;
}

3
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -17,7 +17,6 @@
#include "gk20a/gk20a.h"
#include <nvgpu/enabled.h>
#include <nvgpu/enabled_t19x.h>
#include "common/linux/vgpu/vgpu.h"
#include "vgpu_gv11b.h"

3
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -68,8 +68,7 @@
#include <gv11b/gr_ctx_gv11b.h>
#include <gv11b/ltc_gv11b.h>
#include <gv11b/gv11b_gating_reglist.h>
#include <gv100/gr_gv100.h>
#include <gv11b/gr_gv11b.h>
#include <nvgpu/enabled.h>

6
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -38,8 +38,8 @@ int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
msg.handle = vgpu_get_handle(tsg->g);
p->tsg_id = tsg->tsgid;
p->ch_handle = ch->virt_ctx;
p->subctx_id = ch->t19x.subctx_id;
p->runqueue_sel = ch->t19x.runqueue_sel;
p->subctx_id = ch->subctx_id;
p->runqueue_sel = ch->runqueue_sel;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
if (err) {

10
drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
View File

@@ -1,7 +1,7 @@
/*
* Virtualized GPU
*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -47,10 +47,6 @@
#include "common/linux/scale.h"
#include "common/linux/driver_common.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include <nvgpu_gpuid_t19x.h>
#endif
#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
static inline int vgpu_comm_init(struct platform_device *pdev)
@@ -436,11 +432,9 @@ static int vgpu_init_hal(struct gk20a *g)
gk20a_dbg_info("gp10b detected");
err = vgpu_gp10b_init_hal(g);
break;
#ifdef CONFIG_TEGRA_19x_GPU
case TEGRA_19x_GPUID:
case NVGPU_GPUID_GV11B:
err = vgpu_gv11b_init_hal(g);
break;
#endif
default:
nvgpu_err(g, "no support for %x", ver);
err = -ENODEV;