From f41e5975d880c070f1f60d4acbfb548739f8f699 Mon Sep 17 00:00:00 2001 From: Antony Clince Alex Date: Fri, 13 Nov 2020 14:50:51 +0530 Subject: [PATCH] gpu: nvgpu: add ioctl to configure l2 max_ways_evict_last Add ioctl support to configure and read the max number of lines/ways in a L2 cache set that can be marked as EVICT_LAST. This is accomplished through two new ltc hals: set_l2_max_ways_evict_last, get_l2_max_ways_evict_last. These hals will only be set for nvgpu-next chips. Incase of legacy chips, the IOCTLs will return error -ENOSYS. Generate following litter constants to get the number of sets in a l2 slice and the number of ways in each set: - GPU_LIT_NUM_LTC_LTS_SETS - GPU_LIT_NUM_LTC_LTS_WAYS Add gpu characteritics flag: NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED to allow userspace driver to determine if L2_MAX_WAYS_EVICT_LAST ioctl is supported. Bug 200605474 Change-Id: Id3180f891399f5e128500f3835d762aee59953e0 Signed-off-by: Antony Clince Alex Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2445884 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.c | 8 ++- drivers/gpu/nvgpu/hal/init/hal_tu104_litter.c | 8 ++- drivers/gpu/nvgpu/include/nvgpu/enabled.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 + drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h | 6 ++- .../include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 4 +- .../include/nvgpu/hw/tu104/hw_proj_tu104.h | 4 +- drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 2 + drivers/gpu/nvgpu/os/linux/ioctl_tsg.c | 50 +++++++++++++++++++ include/uapi/linux/nvgpu-ctrl.h | 2 + include/uapi/linux/nvgpu.h | 21 +++++++- 11 files changed, 104 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.c index 78fa93603..b3212a5d3 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b_litter.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -132,6 +132,12 @@ u32 gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_NUM_FBPAS: ret = proj_scal_litter_num_fbpas_v(); break; + case GPU_LIT_NUM_LTC_LTS_SETS: + ret = proj_scal_litter_num_ltc_lts_sets_v(); + break; + case GPU_LIT_NUM_LTC_LTS_WAYS: + ret = proj_scal_litter_num_ltc_lts_ways_v(); + break; /* Hardcode FBPA values other than NUM_FBPAS to 0. */ case GPU_LIT_FBPA_STRIDE: case GPU_LIT_FBPA_BASE: diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104_litter.c b/drivers/gpu/nvgpu/hal/init/hal_tu104_litter.c index e620a70e4..5ae154ace 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104_litter.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104_litter.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -137,6 +137,12 @@ u32 tu104_get_litter_value(struct gk20a *g, int value) case GPU_LIT_SM_SHARED_BASE: ret = proj_sm_shared_base_v(); break; + case GPU_LIT_NUM_LTC_LTS_SETS: + ret = proj_scal_litter_num_ltc_lts_sets_v(); + break; + case GPU_LIT_NUM_LTC_LTS_WAYS: + ret = proj_scal_litter_num_ltc_lts_ways_v(); + break; #ifdef CONFIG_NVGPU_GRAPHICS case GPU_LIT_TWOD_CLASS: ret = FERMI_TWOD_A; diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 1bb23f7b6..e0fdecd92 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -204,6 +204,8 @@ struct gk20a; DEFINE_FLAG(NVGPU_PMU_NEXT_CORE_ENABLED, "PMU NEXT CORE enabled"), \ DEFINE_FLAG(NVGPU_ACR_NEXT_CORE_ENABLED, \ "NEXT CORE availability for acr"), \ + DEFINE_FLAG(NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED, \ + "Set L2 Max Ways Evict Last support"), \ DEFINE_FLAG(NVGPU_MAX_ENABLED_BITS, "Marks max number of flags"), /** diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index c1d8bf204..669db5588 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -265,6 +265,8 @@ struct railgate_stats { #define GPU_LIT_GPC_ADDR_WIDTH 47 #define GPU_LIT_TPC_ADDR_WIDTH 48 #define GPU_LIT_MAX_RUNLISTS_SUPPORTED 49 +#define GPU_LIT_NUM_LTC_LTS_SETS 50 +#define GPU_LIT_NUM_LTC_LTS_WAYS 51 /** @endcond */ /** Macro to get litter values corresponding to the litter defines. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h index bc868d180..1e9006521 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -155,6 +155,10 @@ struct gops_ltc { void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr, u32 *priv_addr_table, u32 *priv_addr_table_index); + int (*set_l2_max_ways_evict_last)(struct gk20a *g, struct nvgpu_tsg *tsg, + u32 num_ways); + int (*get_l2_max_ways_evict_last)(struct gk20a *g, struct nvgpu_tsg *tsg, + u32 *num_ways); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT) #include "include/nvgpu/nvgpu_next_gops_ltc.h" #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 9b26c1d00..f6a15852a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -89,6 +89,8 @@ #define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U) #define proj_scal_litter_num_zcull_banks_v() (0x00000004U) #define proj_scal_litter_num_sm_per_tpc_v() (0x00000002U) +#define proj_scal_litter_num_ltc_lts_sets_v() (0x00000040U) +#define proj_scal_litter_num_ltc_lts_ways_v() (0x00000010U) #define proj_scal_max_gpcs_v() (0x00000020U) #define proj_scal_max_tpc_per_gpc_v() (0x00000008U) #define proj_sm_unique_base_v() (0x00000700U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h index 5a8547dbd..d01225b93 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -91,6 +91,8 @@ #define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U) #define proj_scal_litter_num_zcull_banks_v() (0x00000004U) #define proj_scal_litter_num_sm_per_tpc_v() (0x00000002U) +#define proj_scal_litter_num_ltc_lts_sets_v() (0x00000040U) +#define proj_scal_litter_num_ltc_lts_ways_v() (0x00000010U) #define proj_scal_max_gpcs_v() (0x00000020U) #define proj_scal_max_tpc_per_gpc_v() (0x00000008U) #define proj_sm_unique_base_v() (0x00000700U) diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index dcbc7ba3b..748ac0016 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -291,6 +291,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = { NVGPU_SUPPORT_SMPC_GLOBAL_MODE}, {NVGPU_GPU_FLAGS_SUPPORT_GET_GR_CONTEXT, NVGPU_SUPPORT_GET_GR_CONTEXT}, + {NVGPU_GPU_FLAGS_L2_MAX_WAYS_EVICT_LAST_ENABLED, + NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED}, }; static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c index 4c8a1e20d..e232464ff 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c @@ -645,6 +645,42 @@ static int gk20a_tsg_ioctl_read_single_sm_error_state(struct gk20a *g, return 0; } +static int nvgpu_gpu_ioctl_set_l2_max_ways_evict_last( + struct gk20a *g, struct nvgpu_tsg *tsg, + struct nvgpu_tsg_l2_max_ways_evict_last_args *args) +{ + int err; + + nvgpu_mutex_acquire(&g->dbg_sessions_lock); + if (g->ops.ltc.set_l2_max_ways_evict_last) { + err = g->ops.ltc.set_l2_max_ways_evict_last(g, tsg, + args->max_ways); + } else { + err = -ENOSYS; + } + nvgpu_mutex_release(&g->dbg_sessions_lock); + + return err; +} + +static int nvgpu_gpu_ioctl_get_l2_max_ways_evict_last( + struct gk20a *g, struct nvgpu_tsg *tsg, + struct nvgpu_tsg_l2_max_ways_evict_last_args *args) +{ + int err; + + nvgpu_mutex_acquire(&g->dbg_sessions_lock); + if (g->ops.ltc.get_l2_max_ways_evict_last) { + err = g->ops.ltc.get_l2_max_ways_evict_last(g, tsg, + &args->max_ways); + } else { + err = -ENOSYS; + } + nvgpu_mutex_release(&g->dbg_sessions_lock); + + return err; +} + long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { @@ -788,6 +824,20 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, break; } + case NVGPU_TSG_IOCTL_SET_L2_MAX_WAYS_EVICT_LAST: + { + err = nvgpu_gpu_ioctl_set_l2_max_ways_evict_last(g, tsg, + (struct nvgpu_tsg_l2_max_ways_evict_last_args *)buf); + break; + } + + case NVGPU_TSG_IOCTL_GET_L2_MAX_WAYS_EVICT_LAST: + { + err = nvgpu_gpu_ioctl_get_l2_max_ways_evict_last(g, tsg, + (struct nvgpu_tsg_l2_max_ways_evict_last_args *)buf); + break; + } + default: nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", cmd); diff --git a/include/uapi/linux/nvgpu-ctrl.h b/include/uapi/linux/nvgpu-ctrl.h index d9cbc948f..90f7c62af 100644 --- a/include/uapi/linux/nvgpu-ctrl.h +++ b/include/uapi/linux/nvgpu-ctrl.h @@ -184,6 +184,8 @@ struct nvgpu_gpu_zbc_query_table_args { #define NVGPU_GPU_FLAGS_SUPPORT_GET_GR_CONTEXT (1ULL << 49) /* Additional buffer metadata association supported */ #define NVGPU_GPU_FLAGS_SUPPORT_BUFFER_METADATA (1ULL << 50) +/* Flag to indicate whether configuring L2_MAXEVICTLAST_WAYS is supported */ +#define NVGPU_GPU_FLAGS_L2_MAX_WAYS_EVICT_LAST_ENABLED (1ULL << 51) /* SM LRF ECC is enabled */ #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) /* SM SHM ECC is enabled */ diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 5ea58a13a..114d96ca9 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -72,6 +72,18 @@ struct nvgpu_tsg_read_single_sm_error_state_args { __u64 record_size; }; +/* + * This struct is used to read and configure l2 max evict_last + * setting. + */ +struct nvgpu_tsg_l2_max_ways_evict_last_args { + /* + * Maximum number of ways in a l2 cache set that can be allocated + * with eviction_policy=EVICT_LAST + */ + __u32 max_ways; +}; + #define NVGPU_TSG_IOCTL_BIND_CHANNEL \ _IOW(NVGPU_TSG_IOCTL_MAGIC, 1, int) #define NVGPU_TSG_IOCTL_UNBIND_CHANNEL \ @@ -95,10 +107,17 @@ struct nvgpu_tsg_read_single_sm_error_state_args { #define NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE \ _IOWR(NVGPU_TSG_IOCTL_MAGIC, 12, \ struct nvgpu_tsg_read_single_sm_error_state_args) +#define NVGPU_TSG_IOCTL_SET_L2_MAX_WAYS_EVICT_LAST \ + _IOW(NVGPU_TSG_IOCTL_MAGIC, 13, \ + struct nvgpu_tsg_l2_max_ways_evict_last_args) +#define NVGPU_TSG_IOCTL_GET_L2_MAX_WAYS_EVICT_LAST \ + _IOR(NVGPU_TSG_IOCTL_MAGIC, 14, \ + struct nvgpu_tsg_l2_max_ways_evict_last_args) #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ sizeof(struct nvgpu_tsg_bind_channel_ex_args) + #define NVGPU_TSG_IOCTL_LAST \ - _IOC_NR(NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE) + _IOC_NR(NVGPU_TSG_IOCTL_GET_L2_MAX_WAYS_EVICT_LAST) /* * /dev/nvhost-dbg-gpu device