gpu: nvgpu: build dGPU in safety

Enable build flags for dGPU in safety, when NVGPU_FORCE_DGPU_SAFETY_PROFILE is set. Use libnvgpu-dgpu_safe.exports for dGPU safety build. Add build flags for tu104 HAL initialization (to solve undefined symbols in safety build). Temporarily add non-fusa files needed to build dGPU in safety. related functions will have to move to fusa files. Jira NVGPU-4611 Change-Id: I41db0c039c7f15d9191cdb811b4906e779d5cc88 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310276 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2025-12-23 18:16:01 +03:00 · 2020-03-16 18:00:30 -04:00
parent 872b3946dd
commit f43d5df83a
12 changed files with 101 additions and 33 deletions
--- a/drivers/gpu/nvgpu/Makefile.interface.tmk
+++ b/drivers/gpu/nvgpu/Makefile.interface.tmk
@@ -1,6 +1,6 @@
 ################################### tell Emacs this is a -*- makefile-gmake -*-
 #
-# Copyright (c) 2018, NVIDIA CORPORATION.  All Rights Reserved.
+# Copyright (c) 2018-2020, NVIDIA CORPORATION.  All Rights Reserved.
 #
 # NVIDIA CORPORATION and its licensors retain all intellectual property
 # and proprietary rights in and to this software, related documentation
@@ -16,7 +16,11 @@

 ifdef NV_INTERFACE_FLAG_SHARED_LIBRARY_SECTION
 NV_INTERFACE_NAME             := nvgpu-drv
+ifeq ($(CONFIG_NVGPU_DGPU), 1)
+NV_INTERFACE_EXPORTS         := lib$(NV_INTERFACE_NAME)-dgpu_safe
+else
 NV_INTERFACE_EXPORTS         := lib$(NV_INTERFACE_NAME)_safe
+endif
 NV_INTERFACE_PUBLIC_INCLUDES  := . include
 endif

--- a/drivers/gpu/nvgpu/Makefile.shared.configs
+++ b/drivers/gpu/nvgpu/Makefile.shared.configs
@@ -82,6 +82,34 @@ NVGPU_COMMON_CFLAGS             +=      \
 # NVGPU_COMMON_CFLAGS             +=      \
 # 	-DCONFIG_NVGPU_CTXSW_FW_ERROR_HEADER_TESTING

+ifeq ($(NVGPU_FORCE_DGPU_SAFETY_PROFILE),1)
+
+CONFIG_NVGPU_DGPU               := 1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_DGPU
+
+CONFIG_NVGPU_NVLINK             := 1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_NVLINK
+
+# used by sec2 code
+CONFIG_NVGPU_ENGINE_QUEUE       := 1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_ENGINE_QUEUE
+
+# used in ce_app
+CONFIG_NVGPU_FENCE              := 1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_FENCE
+
+# ce_app uses syncpt (nvgpu_nvhost_syncpt_wait_timeout_ext)
+CONFIG_NVGPU_KERNEL_MODE_SUBMIT := 1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_KERNEL_MODE_SUBMIT
+
+CONFIG_NVGPU_FALCON_NON_FUSA	:= 1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_FALCON_NON_FUSA
+
+# nvgpu_semaphore_get_value
+CONFIG_NVGPU_SW_SEMAPHORE :=1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_SW_SEMAPHORE
+endif
+
 endif

 CONFIG_NVGPU_TEGRA_FUSE		:= 1
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -318,6 +318,16 @@ srcs += hal/init/hal_gp10b.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c
+else
+ifeq ($(CONFIG_NVGPU_DGPU),1)
+# non-FUSA files needed to build dGPU in safety
+srcs += hal/gr/falcon/gr_falcon_gm20b.c \
+	hal/fuse/fuse_gm20b.c \
+	hal/fb/fb_gp106.c \
+	hal/falcon/falcon_gk20a.c \
+	hal/bus/bus_gk20a.c \
+	hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c
+endif
 endif

 ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
--- a/drivers/gpu/nvgpu/common/fifo/channel.c
+++ b/drivers/gpu/nvgpu/common/fifo/channel.c
@@ -1478,8 +1478,9 @@ void nvgpu_channel_update(struct nvgpu_channel *c)
 	if (nvgpu_is_powered_off(c->g)) { /* shutdown case */
 		return;
 	}
-
+#ifdef CONFIG_NVGPU_TRACE
 	trace_nvgpu_channel_update(c->chid);
+#endif
 	/* A queued channel is always checked for job cleanup. */
 	channel_worker_enqueue(c);
 }
--- a/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.h
@@ -1,7 +1,7 @@
 /*
 * GM20B FUSE
 *
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -32,7 +32,8 @@

 struct gk20a;

-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) || defined(CONFIG_NVGPU_DGPU)
+/* FIXME: below functions are needed for dGPU safety build. */
 int gm20b_fuse_check_priv_security(struct gk20a *g);
 u32 gm20b_fuse_status_opt_gpc(struct gk20a *g);
 #endif
--- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -69,21 +69,3 @@ u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g,
 	return gr_gpc0_fs_gpc_num_available_zculls_v(tmp);
 }
 #endif
-
-u32 gm20b_gr_config_get_gpc_mask(struct gk20a *g,
-	struct nvgpu_gr_config *config)
-{
-	u32 val;
-	u32 tpc_cnt = nvgpu_gr_config_get_max_gpc_count(config);
-
-	/*
-	 * For register NV_FUSE_STATUS_OPT_GPC a set bit with index i indicates
-	 * corresponding GPC is floorswept
-	 * But for s/w mask a set bit means GPC is enabled and it is disabled
-	 * otherwise
-	 * Hence toggle the bits of register value to get s/w mask
-	 */
-	val = g->ops.fuse.fuse_status_opt_gpc(g);
-
-	return (~val) & nvgpu_safe_sub_u32(BIT32(tpc_cnt), 1U);
-}
--- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -35,9 +35,9 @@ u32 gm20b_gr_config_get_tpc_count_in_gpc(struct gk20a *g,
 u32 gm20b_gr_config_get_pes_tpc_mask(struct gk20a *g,
 	struct nvgpu_gr_config *config, u32 gpc_index, u32 pes_index);
 u32 gm20b_gr_config_get_pd_dist_skip_table_size(void);
-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 u32 gm20b_gr_config_get_gpc_mask(struct gk20a *g,
 	struct nvgpu_gr_config *config);
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 int gm20b_gr_config_init_sm_id_table(struct gk20a *g,
 	struct nvgpu_gr_config *gr_config);
 #ifdef CONFIG_NVGPU_GRAPHICS
--- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -72,3 +72,21 @@ u32 gm20b_gr_config_get_pd_dist_skip_table_size(void)
 {
 	return gr_pd_dist_skip_table__size_1_v();
 }
+
+u32 gm20b_gr_config_get_gpc_mask(struct gk20a *g,
+	struct nvgpu_gr_config *config)
+{
+	u32 val;
+	u32 tpc_cnt = nvgpu_gr_config_get_max_gpc_count(config);
+
+	/*
+	 * For register NV_FUSE_STATUS_OPT_GPC a set bit with index i indicates
+	 * corresponding GPC is floorswept
+	 * But for s/w mask a set bit means GPC is enabled and it is disabled
+	 * otherwise
+	 * Hence toggle the bits of register value to get s/w mask
+	 */
+	val = g->ops.fuse.fuse_status_opt_gpc(g);
+
+	return (~val) & nvgpu_safe_sub_u32(BIT32(tpc_cnt), 1U);
+}
--- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -42,10 +42,11 @@ void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g,
 	struct nvgpu_mem *ctx_mem, u64 addr);
 void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g,
 	struct nvgpu_mem *ctx_mem);
-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) || defined(CONFIG_NVGPU_DGPU)
+/* FIXME: below function is used in dGPU safety build. */
 void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g,
 	struct nvgpu_mem *ctx_mem);
-#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
+#endif
 #ifdef CONFIG_NVGPU_GRAPHICS
 void gm20b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem,
 	u64 addr);
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -112,8 +112,10 @@
 #include "hal/fifo/pbdma_status_gm20b.h"
 #include "hal/fifo/ctxsw_timeout_gv11b.h"
 #include "hal/gr/ecc/ecc_gv11b.h"
+#ifdef CONFIG_NVGPU_FECS_TRACE
 #include "hal/gr/fecs_trace/fecs_trace_gm20b.h"
 #include "hal/gr/fecs_trace/fecs_trace_gv11b.h"
+#endif
 #include "hal/gr/falcon/gr_falcon_gm20b.h"
 #include "hal/gr/falcon/gr_falcon_gp10b.h"
 #include "hal/gr/falcon/gr_falcon_gv11b.h"
@@ -134,25 +136,33 @@
 #include "hal/gr/intr/gr_intr_gp10b.h"
 #include "hal/gr/intr/gr_intr_gv11b.h"
 #include "hal/gr/intr/gr_intr_tu104.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
 #include "hal/gr/hwpm_map/hwpm_map_gv100.h"
+#endif
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
 #include "hal/gr/gr/gr_gk20a.h"
 #include "hal/gr/gr/gr_gm20b.h"
 #include "hal/gr/gr/gr_gp10b.h"
 #include "hal/gr/gr/gr_gv11b.h"
 #include "hal/gr/gr/gr_gv100.h"
 #include "hal/gr/gr/gr_tu104.h"
+#endif
 #include "hal/pmu/pmu_gk20a.h"
+#ifdef CONFIG_NVGPU_LS_PMU
 #include "hal/pmu/pmu_gm20b.h"
+#endif
 #include "hal/pmu/pmu_gp10b.h"
 #include "hal/pmu/pmu_gv11b.h"
 #include "hal/pmu/pmu_tu104.h"
 #include "hal/falcon/falcon_gk20a.h"
 #include "hal/nvdec/nvdec_tu104.h"
 #include "hal/gsp/gsp_tu104.h"
+#ifdef CONFIG_NVGPU_DEBUGGER
 #include "hal/perf/perf_gv11b.h"
+#endif
 #ifdef CONFIG_NVGPU_DGPU
 #include "hal/sec2/sec2_tu104.h"
 #endif
@@ -180,7 +190,9 @@
 #include "hal/fifo/channel_gm20b.h"
 #include "hal/fifo/channel_gv11b.h"
 #include "hal/fifo/channel_gv100.h"
+#ifdef CONFIG_NVGPU_CLK_ARB
 #include "common/clk_arb/clk_arb_gv100.h"
+#endif

 #include "hal/clk/clk_tu104.h"
 #include "hal/clk/clk_mon_tu104.h"
@@ -593,7 +605,6 @@ static const struct gpu_ops tu104_ops = {
 				gm20b_gr_init_fe_pwr_mode_force_on,
 			.override_context_reset =
 				gm20b_gr_init_override_context_reset,
-			.preemption_state = gv11b_gr_init_preemption_state,
 			.fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout,
 			.load_method_init = gm20b_gr_init_load_method_init,
 			.commit_global_timeslice =
@@ -658,6 +669,7 @@ static const struct gpu_ops tu104_ops = {
 			.wait_initialized = nvgpu_gr_wait_initialized,
 #endif
 #ifdef CONFIG_NVGPU_GRAPHICS
+			.preemption_state = gv11b_gr_init_preemption_state,
 			.get_ctx_attrib_cb_size =
 				gp10b_gr_init_get_ctx_attrib_cb_size,
 			.commit_cbes_reserve =
@@ -993,7 +1005,9 @@ static const struct gpu_ops tu104_ops = {
 		.intr_enable = gv11b_pbdma_intr_enable,
 		.acquire_val = gm20b_pbdma_acquire_val,
 		.get_signature = gp10b_pbdma_get_signature,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 		.dump_status = gm20b_pbdma_dump_status,
+#endif
 		.handle_intr = gm20b_pbdma_handle_intr,
 		.handle_intr_0 = gv11b_pbdma_handle_intr_0,
 		.handle_intr_1 = gv11b_pbdma_handle_intr_1,
@@ -1206,7 +1220,9 @@ static const struct gpu_ops tu104_ops = {
 		.init_therm_support = nvgpu_init_therm_support,
 		/* PROD values match with H/W INIT values */
 		.init_elcg_mode = gv11b_therm_init_elcg_mode,
+#ifdef CONFIG_NVGPU_NON_FUSA
 		.init_blcg_mode = gm20b_therm_init_blcg_mode,
+#endif
 		.elcg_init_idle_filters = NULL,
 #ifdef CONFIG_NVGPU_LS_PMU
 		.get_internal_sensor_limits =
@@ -1317,7 +1333,9 @@ static const struct gpu_ops tu104_ops = {
 	.mc = {
 		.get_chip_details = gm20b_get_chip_details,
 		.intr_mask = intr_tu104_mask,
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 		.intr_enable = NULL,
+#endif
 		.intr_stall_unit_config = intr_tu104_stall_unit_config,
 		.intr_nonstall_unit_config = intr_tu104_nonstall_unit_config,
 		.isr_stall = mc_gp10b_isr_stall,
@@ -1332,7 +1350,9 @@ static const struct gpu_ops tu104_ops = {
 		.disable = gm20b_mc_disable,
 		.reset = gm20b_mc_reset,
 		.is_intr1_pending = NULL,
+#ifdef CONFIG_NVGPU_NON_FUSA
 		.log_pending_intrs = intr_tu104_log_pending_intrs,
+#endif
 		.is_intr_hub_pending = intr_tu104_is_intr_hub_pending,
 		.is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending,
 		.is_stall_and_eng_intr_pending =
@@ -1442,9 +1462,9 @@ static const struct gpu_ops tu104_ops = {
 #ifdef CONFIG_NVGPU_FALCON_DEBUG
 		.dump_falcon_stats = gk20a_falcon_dump_stats,
 #endif
-#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
 		.clear_halt_interrupt_status =
 			gk20a_falcon_clear_halt_interrupt_status,
+#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
 		.copy_from_dmem = gk20a_falcon_copy_from_dmem,
 		.copy_from_imem = gk20a_falcon_copy_from_imem,
 		.get_falcon_ctls = gk20a_falcon_get_ctls,
--- a/drivers/gpu/nvgpu/hal/mc/mc_gv100.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gv100.c
@@ -79,9 +79,11 @@ u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
 	case NVGPU_UNIT_BLG:
 		mask = mc_enable_blg_enabled_f();
 		break;
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	case NVGPU_UNIT_PWR:
 		mask = mc_enable_pwr_enabled_f();
 		break;
+#endif
 	case NVGPU_UNIT_NVDEC:
 		mask = mc_enable_nvdec_enabled_f();
 		break;
--- a/drivers/gpu/nvgpu/include/nvgpu/class.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/class.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -96,7 +96,8 @@
 #define	TURING_A			0xC597U
 #endif

-#ifdef CONFIG_NVGPU_NON_FUSA
+#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_DGPU)
+/* FIXME: below defines are used in dGPU safety build. */
 #define	MAXWELL_COMPUTE_B		0xB1C0U
 #define	PASCAL_COMPUTE_A		0xC0C0U
 #define	TURING_CHANNEL_GPFIFO_A		0xC46FU