gpu: nvgpu: remove BIT macros from header file

Jira EVLR-472

Change-Id: I791f4647330bfea931da7ea6ffed95b8334b4817
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1172097
(cherry picked from commit 5b41dea91208bba53ba87be1e732c85d177a8ad3)
Reviewed-on: http://git-master/r/1177825
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
This commit is contained in:
Thomas Fleury
2016-06-27 16:59:54 -07:00
committed by Deepak Nibade
parent 00a092b729
commit f48a806cf0

View File

@@ -46,9 +46,9 @@
#define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2) #define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2)
/* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */ /* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */
#define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP BIT(1) #define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP (1 << 1)
/* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */ /* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */
#define NVGPU_COMPUTE_PREEMPTION_MODE_CILP BIT(2) #define NVGPU_COMPUTE_PREEMPTION_MODE_CILP (1 << 2)
/* SM LRF ECC is enabled */ /* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)