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gpu: nvgpu: PS35: Clk Prog Boardobj changes

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1. Add VBIOS PS3.5 Clk programming table parsing code.
2. Update pmuifclk.h to match R400 pmu ucode pmuifclk.h
3. New clk_prog boardobj types have been added to support
   PS3.5 and to match the pmu ucode side changes
4. Add PS3.5 related construct and pmudatainit fops
5. PS3.5 clk programming table has secondary VF curve entries.
   Though these entries are currently marked as invalid for
   all SKUs, we need to add them to match struct sizes on PMU.
6. The pmuifclk.h nvgpu<->pmu interface changes needed for
   Turing(PS3.5) are NOT compatible with GV100 branched ucode.
   The secondary VF curve entries added for PS3.5 increase the
   entrysize breaking compatibility with GV100.
7. This change is therefore dependant on GV100 PMU ucode changes
   which increase the entrysize on GV100 pmu side.

JIRA NVGPU-1153

Change-Id: I868e503f87731442aae6503872ade4c208831d34
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1842627
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
tkudav
2018-09-24 14:14:51 +05:30
committed by mobile promotions
parent 69b46a6174
commit f4bd7552b3
5 changed files with 782 additions and 97 deletions
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18
drivers/gpu/nvgpu/ctrl/ctrlclk.h
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@@ -60,10 +60,15 @@
#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFFU
#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF
#define CTRL_CLK_CLK_PROG_TYPE_3X 0x00U
#define CTRL_CLK_CLK_PROG_TYPE_1X 0x01U
#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x02U
#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x03U
#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x04U
#define CTRL_CLK_CLK_PROG_TYPE_35 0x05U
#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER 0x06U
#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER_RATIO 0x07U
#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER_TABLE 0x08U
#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255U
/*!
@@ -75,6 +80,7 @@
#define CTRL_CLK_PROG_1X_SOURCE_INVALID 255U
#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4U
#define CTRL_CLK_CLK_PROG_35_MASTER_SEC_VF_ENTRY_VOLTRAIL_MAX 1U
#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6U
#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255U
@@ -110,6 +116,18 @@ struct ctrl_clk_clk_prog_1x_master_vf_entry {
u8 vf_point_idx_last;
};
struct ctrl_clk_clk_prog_35_master_sec_vf_entry {
u8 vfe_idx;
u8 dvco_offset_vfe_idx;
u8 vf_point_idx_first;
u8 vf_point_idx_last;
};
struct ctrl_clk_clk_prog_35_master_sec_vf_entry_voltrail {
struct ctrl_clk_clk_prog_35_master_sec_vf_entry sec_vf_entries[
CTRL_CLK_CLK_PROG_35_MASTER_SEC_VF_ENTRY_VOLTRAIL_MAX];
};
struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry {
u8 clk_dom_idx;
u8 ratio;