diff --git a/drivers/gpu/nvgpu/common/fbp/fbp.c b/drivers/gpu/nvgpu/common/fbp/fbp.c
index 2057f108e..9c013d1a6 100644
--- a/drivers/gpu/nvgpu/common/fbp/fbp.c
+++ b/drivers/gpu/nvgpu/common/fbp/fbp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -34,7 +34,7 @@ int nvgpu_fbp_init_support(struct gk20a *g)
 	u32 fbp_en_mask;
 #ifdef CONFIG_NVGPU_NON_FUSA
 	u32 max_ltc_per_fbp;
-	u32 rop_l2_all_en;
+	u32 l2_all_en_mask;
 	unsigned long i;
 	unsigned long fbp_en_mask_tmp;
 	u32 tmp;
@@ -70,22 +70,22 @@ int nvgpu_fbp_init_support(struct gk20a *g)
 	fbp->fbp_en_mask = fbp_en_mask;
 
 #ifdef CONFIG_NVGPU_NON_FUSA
-	fbp->fbp_rop_l2_en_mask =
+	fbp->fbp_l2_en_mask =
 		nvgpu_kzalloc(g,
 			nvgpu_safe_mult_u64(fbp->max_fbps_count, sizeof(u32)));
-	if (fbp->fbp_rop_l2_en_mask == NULL) {
+	if (fbp->fbp_l2_en_mask == NULL) {
 		nvgpu_kfree(g, fbp);
 		return -ENOMEM;
 	}
 
 	fbp_en_mask_tmp = fbp_en_mask;
 	max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g);
-	rop_l2_all_en = nvgpu_safe_sub_u32(BIT32(max_ltc_per_fbp), 1U);
+	l2_all_en_mask = nvgpu_safe_sub_u32(BIT32(max_ltc_per_fbp), 1U);
 
-	/* mask of Rop_L2 for each FBP */
+	/* get active L2 mask per FBP */
 	for_each_set_bit(i, &fbp_en_mask_tmp, fbp->max_fbps_count) {
-		tmp = g->ops.fuse.fuse_status_opt_rop_l2_fbp(g, i);
-		fbp->fbp_rop_l2_en_mask[i] = rop_l2_all_en ^ tmp;
+		tmp = g->ops.fuse.fuse_status_opt_l2_fbp(g, i);
+		fbp->fbp_l2_en_mask[i] = l2_all_en_mask ^ tmp;
 	}
 #endif
 
@@ -99,7 +99,7 @@ void nvgpu_fbp_remove_support(struct gk20a *g)
 	struct nvgpu_fbp *fbp = g->fbp;
 
 	if (fbp != NULL) {
-		nvgpu_kfree(g, fbp->fbp_rop_l2_en_mask);
+		nvgpu_kfree(g, fbp->fbp_l2_en_mask);
 		nvgpu_kfree(g, fbp);
 	}
 
@@ -122,9 +122,9 @@ u32 nvgpu_fbp_get_num_fbps(struct nvgpu_fbp *fbp)
 	return fbp->num_fbps;
 }
 
-u32 *nvgpu_fbp_get_rop_l2_en_mask(struct nvgpu_fbp *fbp)
+u32 *nvgpu_fbp_get_l2_en_mask(struct nvgpu_fbp *fbp)
 {
-	return fbp->fbp_rop_l2_en_mask;
+	return fbp->fbp_l2_en_mask;
 }
 #endif
 
diff --git a/drivers/gpu/nvgpu/common/fbp/fbp_priv.h b/drivers/gpu/nvgpu/common/fbp/fbp_priv.h
index 1442e4776..a64a0d450 100644
--- a/drivers/gpu/nvgpu/common/fbp/fbp_priv.h
+++ b/drivers/gpu/nvgpu/common/fbp/fbp_priv.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,7 +27,7 @@ struct nvgpu_fbp {
 	u32 num_fbps;
 	u32 max_fbps_count;
 	u32 fbp_en_mask;
-	u32 *fbp_rop_l2_en_mask;
+	u32 *fbp_l2_en_mask;
 };
 
 #endif /* NVGPU_FBP_PRIV_H */
diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
index 3e54f2b8f..3bfc89db9 100644
--- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c
+++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
@@ -157,7 +157,7 @@ int nvgpu_init_gr_manager(struct gk20a *g)
 	gpu_instance->fbp_en_mask = nvgpu_fbp_get_fbp_en_mask(g->fbp);
 #ifdef CONFIG_NVGPU_NON_FUSA
 	gpu_instance->num_fbp = nvgpu_fbp_get_num_fbps(g->fbp);
-	gpu_instance->fbp_rop_l2_en_mask = nvgpu_fbp_get_rop_l2_en_mask(g->fbp);
+	gpu_instance->fbp_l2_en_mask = nvgpu_fbp_get_l2_en_mask(g->fbp);
 #endif
 
 	g->mig.current_gr_syspipe_id = NVGPU_MIG_INVALID_GR_SYSPIPE_ID;
@@ -702,14 +702,14 @@ u32 nvgpu_grmgr_get_fbp_en_mask(struct gk20a *g, u32 gpu_instance_id)
 	return U32_MAX;
 }
 
-u32 *nvgpu_grmgr_get_fbp_rop_l2_en_mask(struct gk20a *g, u32 gpu_instance_id)
+u32 *nvgpu_grmgr_get_fbp_l2_en_mask(struct gk20a *g, u32 gpu_instance_id)
 {
 	struct nvgpu_gpu_instance *gpu_instance;
 
 	if (gpu_instance_id < g->mig.num_gpu_instances) {
 		gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
 
-		return gpu_instance->fbp_rop_l2_en_mask;
+		return gpu_instance->fbp_l2_en_mask;
 	}
 
 	nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/common/vgpu/fbp/fbp_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/fbp/fbp_vgpu.c
index 1b31a6a53..321c881d2 100644
--- a/drivers/gpu/nvgpu/common/vgpu/fbp/fbp_vgpu.c
+++ b/drivers/gpu/nvgpu/common/vgpu/fbp/fbp_vgpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -46,15 +46,15 @@ int vgpu_fbp_init_support(struct gk20a *g)
 	fbp->max_fbps_count = priv->constants.num_fbps;
 	fbp->fbp_en_mask = priv->constants.fbp_en_mask;
 
-	fbp->fbp_rop_l2_en_mask =
+	fbp->fbp_l2_en_mask =
 		nvgpu_kzalloc(g, fbp->max_fbps_count * sizeof(u32));
-	if (fbp->fbp_rop_l2_en_mask == NULL) {
+	if (fbp->fbp_l2_en_mask == NULL) {
 		nvgpu_kfree(g, fbp);
 		return -ENOMEM;
 	}
 
 	for (i = 0U; i < fbp->max_fbps_count; i++) {
-		fbp->fbp_rop_l2_en_mask[i] = priv->constants.l2_en_mask[i];
+		fbp->fbp_l2_en_mask[i] = priv->constants.l2_en_mask[i];
 	}
 
 	g->fbp = fbp;
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c
index bf2f5576f..e3777ee31 100644
--- a/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.c
@@ -1,7 +1,7 @@
 /*
  * GA100 FUSE
  *
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,7 @@
 
 #include <nvgpu/hw/ga100/hw_fuse_ga100.h>
 
-u32 ga100_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
+u32 ga100_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp)
 {
 	return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
 }
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h
index 603c13b4d..0c27d1f2e 100644
--- a/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga100.h
@@ -1,7 +1,7 @@
 /*
  * GA100 FUSE
  *
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,7 +27,7 @@
 
 struct gk20a;
 
-u32 ga100_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
+u32 ga100_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp);
 int ga100_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi);
 int ga100_read_ucode_version(struct gk20a *g, u32 falcon_id,
 		u32 *ucode_version);
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c
index 346d85336..07d5a9313 100644
--- a/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c
@@ -93,9 +93,9 @@ u32 ga10b_fuse_status_opt_fbp(struct gk20a *g)
 	return nvgpu_readl(g, fuse_status_opt_fbp_r());
 }
 
-u32 ga10b_fuse_status_opt_rop_gpc(struct gk20a *g, u32 fbp)
+u32 ga10b_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp)
 {
-	return nvgpu_readl(g, fuse_status_opt_rop_gpc_r(fbp));
+	return nvgpu_readl(g, fuse_ctrl_opt_ltc_fbp_r(fbp));
 }
 
 u32 ga10b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc)
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h
index 9c8e5d3b6..95e8eccef 100644
--- a/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h
@@ -36,7 +36,7 @@ bool ga10b_fuse_is_opt_feature_override_disable(struct gk20a *g);
 u32 ga10b_fuse_status_opt_gpc(struct gk20a *g);
 u32 ga10b_fuse_status_opt_fbio(struct gk20a *g);
 u32 ga10b_fuse_status_opt_fbp(struct gk20a *g);
-u32 ga10b_fuse_status_opt_rop_gpc(struct gk20a *g, u32 fbp);
+u32 ga10b_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp);
 u32 ga10b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
 void ga10b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
 u32 ga10b_fuse_opt_priv_sec_en(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.h b/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.h
index bf3d910f4..dd181a23f 100644
--- a/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B FUSE
  *
- * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -34,7 +34,7 @@ u32 gm20b_fuse_status_opt_gpc(struct gk20a *g);
 #endif
 u32 gm20b_fuse_status_opt_fbio(struct gk20a *g);
 u32 gm20b_fuse_status_opt_fbp(struct gk20a *g);
-u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
+u32 gm20b_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp);
 u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
 void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
 u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b_fusa.c
index 17692a462..323d9cd94 100644
--- a/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fuse/fuse_gm20b_fusa.c
@@ -1,7 +1,7 @@
 /*
  * GM20B FUSE
  *
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -42,7 +42,7 @@ u32 gm20b_fuse_status_opt_fbp(struct gk20a *g)
 	return nvgpu_readl(g, fuse_status_opt_fbp_r());
 }
 
-u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
+u32 gm20b_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp)
 {
 	return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
 }
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
index b0e69aea3..5bc5e1d95 100644
--- a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
@@ -296,7 +296,7 @@ static int ga10b_grmgr_get_gpu_instance(struct gk20a *g,
 	u32 max_subctx_count = g->ops.gr.init.get_max_subctx_count();
 	u32 max_fbps_count = g->mig.max_fbps_count;
 	u32 physical_fbp_en_mask = g->mig.gpu_instance[0].fbp_en_mask;
-	u32 *physical_fbp_rop_l2_en_mask = g->mig.gpu_instance[0].fbp_rop_l2_en_mask;
+	u32 *physical_fbp_l2_en_mask = g->mig.gpu_instance[0].fbp_l2_en_mask;
 
 	if ((mig_gpu_instance_config == NULL) || (num_gpc > NVGPU_MIG_MAX_GPCS)) {
 		nvgpu_err(g,"mig_gpu_instance_config NULL "
@@ -564,12 +564,12 @@ static int ga10b_grmgr_get_gpu_instance(struct gk20a *g,
 			}
 		}
 
-		gpu_instance[index].fbp_rop_l2_en_mask =
+		gpu_instance[index].fbp_l2_en_mask =
 			nvgpu_kzalloc(g,
 				nvgpu_safe_mult_u64(max_fbps_count, sizeof(u32)));
-		if (gpu_instance[index].fbp_rop_l2_en_mask == NULL) {
+		if (gpu_instance[index].fbp_l2_en_mask == NULL) {
 			nvgpu_err(g,
-				"gpu_instance[%d].fbp_rop_l2_en_mask aloc failed",
+				"gpu_instance[%d].fbp_l2_en_mask aloc failed",
 				index);
 			err = -ENOMEM;
 			goto exit;
@@ -577,8 +577,8 @@ static int ga10b_grmgr_get_gpu_instance(struct gk20a *g,
 
 		if (gpu_instance[index].is_memory_partition_supported == false) {
 			u32 physical_fb_id, logical_fb_id;
-			u32 *logical_fbp_rop_l2_en_mask =
-				gpu_instance[index].fbp_rop_l2_en_mask;
+			u32 *logical_fbp_l2_en_mask =
+				gpu_instance[index].fbp_l2_en_mask;
 
 			gpu_instance[index].num_fbp = g->mig.gpu_instance[0].num_fbp;
 			gpu_instance[index].fbp_en_mask =
@@ -590,8 +590,8 @@ static int ga10b_grmgr_get_gpu_instance(struct gk20a *g,
 						(physical_fb_id < max_fbps_count));
 					++physical_fb_id) {
 				if (physical_fbp_en_mask & BIT32(physical_fb_id)) {
-					logical_fbp_rop_l2_en_mask[logical_fb_id] =
-						physical_fbp_rop_l2_en_mask[physical_fb_id];
+					logical_fbp_l2_en_mask[logical_fb_id] =
+						physical_fbp_l2_en_mask[physical_fb_id];
 					++logical_fb_id;
 				}
 			}
@@ -922,13 +922,13 @@ int ga10b_grmgr_remove_gr_manager(struct gk20a *g)
 	err |= g->ops.fb.config_veid_smc_map(g, false);
 	err |= g->ops.fb.set_remote_swizid(g, false);
 
-	/* Free only MIG instance fbp_rop_l2_en_mask */
+	/* Free only MIG instance fbp_l2_en_mask */
 	for (index = 1U; index  < g->mig.num_gpu_instances; index++) {
-		if (g->mig.gpu_instance[index].fbp_rop_l2_en_mask !=
+		if (g->mig.gpu_instance[index].fbp_l2_en_mask !=
 				NULL) {
 			nvgpu_kfree(g,
-				g->mig.gpu_instance[index].fbp_rop_l2_en_mask);
-			g->mig.gpu_instance[index].fbp_rop_l2_en_mask = NULL;
+				g->mig.gpu_instance[index].fbp_l2_en_mask);
+			g->mig.gpu_instance[index].fbp_l2_en_mask = NULL;
 			g->mig.gpu_instance[index].num_fbp = 0U;
 			g->mig.gpu_instance[index].fbp_en_mask = 0U;
 		}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index 3e3adb5fa..14c2c59b4 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -1617,7 +1617,7 @@ static const struct gops_fuse ga100_ops_fuse = {
 	.is_opt_feature_override_disable = ga10b_fuse_is_opt_feature_override_disable,
 	.fuse_status_opt_fbio = ga10b_fuse_status_opt_fbio,
 	.fuse_status_opt_fbp = ga10b_fuse_status_opt_fbp,
-	.fuse_status_opt_rop_l2_fbp = ga100_fuse_status_opt_rop_l2_fbp,
+	.fuse_status_opt_l2_fbp = ga100_fuse_status_opt_l2_fbp,
 	.fuse_status_opt_gpc = ga10b_fuse_status_opt_gpc,
 	.fuse_status_opt_tpc_gpc = ga10b_fuse_status_opt_tpc_gpc,
 	.fuse_ctrl_opt_tpc_gpc = ga10b_fuse_ctrl_opt_tpc_gpc,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index 76ce838f7..60be8a1e3 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -1577,8 +1577,7 @@ static const struct gops_fuse ga10b_ops_fuse = {
 	.is_opt_feature_override_disable = ga10b_fuse_is_opt_feature_override_disable,
 	.fuse_status_opt_fbio = ga10b_fuse_status_opt_fbio,
 	.fuse_status_opt_fbp = ga10b_fuse_status_opt_fbp,
-	/* Update hal for ROP in GPC - NVGPU-4668 */
-	.fuse_status_opt_rop_l2_fbp = ga10b_fuse_status_opt_rop_gpc,
+	.fuse_status_opt_l2_fbp = ga10b_fuse_status_opt_l2_fbp,
 	.fuse_status_opt_tpc_gpc = ga10b_fuse_status_opt_tpc_gpc,
 	.fuse_ctrl_opt_tpc_gpc = ga10b_fuse_ctrl_opt_tpc_gpc,
 	.fuse_opt_sec_debug_en = ga10b_fuse_opt_sec_debug_en,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index 9912f7a70..7861f2c09 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -1026,7 +1026,7 @@ static const struct gops_fuse gm20b_ops_fuse = {
 	.check_priv_security = gm20b_fuse_check_priv_security,
 	.fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
 	.fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
-	.fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+	.fuse_status_opt_l2_fbp = gm20b_fuse_status_opt_l2_fbp,
 	.fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
 	.fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
 	.fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index be13033b1..4360a04b7 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -1124,7 +1124,7 @@ static const struct gops_fuse gp10b_ops_fuse = {
 	.is_opt_feature_override_disable = gp10b_fuse_is_opt_feature_override_disable,
 	.fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
 	.fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
-	.fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+	.fuse_status_opt_l2_fbp = gm20b_fuse_status_opt_l2_fbp,
 	.fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
 	.fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
 	.fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index ab3f4f43a..c0c8e960a 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -1402,7 +1402,7 @@ static const struct gops_fuse gv11b_ops_fuse = {
 	.is_opt_feature_override_disable = gp10b_fuse_is_opt_feature_override_disable,
 	.fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
 	.fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
-	.fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+	.fuse_status_opt_l2_fbp = gm20b_fuse_status_opt_l2_fbp,
 	.fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
 	.fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
 	.fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 91329c112..3f343881d 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1504,7 +1504,7 @@ static const struct gops_fuse tu104_ops_fuse = {
 	.is_opt_feature_override_disable = gp10b_fuse_is_opt_feature_override_disable,
 	.fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
 	.fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
-	.fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+	.fuse_status_opt_l2_fbp = gm20b_fuse_status_opt_l2_fbp,
 	.fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc,
 	.fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
 	.fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
index 9322f6ac6..d78ab46fa 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
@@ -1023,7 +1023,7 @@ static const struct gops_fuse vgpu_ga10b_ops_fuse = {
 	.is_opt_feature_override_disable = NULL,
 	.fuse_status_opt_fbio = NULL,
 	.fuse_status_opt_fbp = NULL,
-	.fuse_status_opt_rop_l2_fbp = NULL,
+	.fuse_status_opt_l2_fbp = NULL,
 	.fuse_status_opt_tpc_gpc = NULL,
 	.fuse_ctrl_opt_tpc_gpc = NULL,
 	.fuse_opt_sec_debug_en = NULL,
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
index 0fc1d1fd8..b702dc328 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
@@ -998,7 +998,7 @@ static const struct gops_fuse vgpu_gv11b_ops_fuse = {
 	.is_opt_feature_override_disable = NULL,
 	.fuse_status_opt_fbio = NULL,
 	.fuse_status_opt_fbp = NULL,
-	.fuse_status_opt_rop_l2_fbp = NULL,
+	.fuse_status_opt_l2_fbp = NULL,
 	.fuse_status_opt_tpc_gpc = NULL,
 	.fuse_ctrl_opt_tpc_gpc = NULL,
 	.fuse_opt_sec_debug_en = NULL,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fbp.h b/drivers/gpu/nvgpu/include/nvgpu/fbp.h
index a7c1c7be4..efcf3909d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fbp.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fbp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -99,7 +99,7 @@ u32 nvgpu_fbp_get_fbp_en_mask(struct nvgpu_fbp *fbp);
 
 #ifdef CONFIG_NVGPU_NON_FUSA
 u32 nvgpu_fbp_get_num_fbps(struct nvgpu_fbp *fbp);
-u32 *nvgpu_fbp_get_rop_l2_en_mask(struct nvgpu_fbp *fbp);
+u32 *nvgpu_fbp_get_l2_en_mask(struct nvgpu_fbp *fbp);
 #endif
 
 /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h
index c9935d828..561071991 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h
@@ -119,7 +119,7 @@ struct gops_fuse {
 	 *
 	 * @return fuse value read from NV_FUSE_STATUS_OPT_ROP_L2_FBP.
 	 */
-	u32 (*fuse_status_opt_rop_l2_fbp)(struct gk20a *g, u32 fbp);
+	u32 (*fuse_status_opt_l2_fbp)(struct gk20a *g, u32 fbp);
 
 	/**
 	 * @brief Read NV_FUSE_STATUS_OPT_TPC_GPC fuse.
diff --git a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
index dabcaf2d9..fc8148f73 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
@@ -57,7 +57,7 @@ u32 nvgpu_grmgr_get_gr_logical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
 u32 nvgpu_grmgr_get_num_fbps(struct gk20a *g, u32 gpu_instance_id);
 u32 nvgpu_grmgr_get_fbp_en_mask(struct gk20a *g, u32 gpu_instance_id);
-u32 *nvgpu_grmgr_get_fbp_rop_l2_en_mask(struct gk20a *g, u32 gpu_instance_id);
+u32 *nvgpu_grmgr_get_fbp_l2_en_mask(struct gk20a *g, u32 gpu_instance_id);
 
 static inline bool nvgpu_grmgr_is_mig_type_gpu_instance(
 		struct nvgpu_gpu_instance *gpu_instance)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h
index e6798c13c..7e5d4a5fe 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h
@@ -62,10 +62,10 @@
 #define fuse_status_opt_gpc_r()                                    (0x00820c1cU)
 #define fuse_status_opt_tpc_gpc_r(i)\
 		(nvgpu_safe_add_u32(0x00820c38U, nvgpu_safe_mult_u32((i), 4U)))
-#define fuse_status_opt_rop_gpc_r(i)\
-		(nvgpu_safe_add_u32(0x00822880U, nvgpu_safe_mult_u32((i), 4U)))
 #define fuse_ctrl_opt_tpc_gpc_r(i)\
 		(nvgpu_safe_add_u32(0x00820838U, nvgpu_safe_mult_u32((i), 4U)))
+#define fuse_ctrl_opt_ltc_fbp_r(i)\
+		(nvgpu_safe_add_u32(0x00820970U, nvgpu_safe_mult_u32((i), 4U)))
 #define fuse_status_opt_fbio_r()                                   (0x00820c14U)
 #define fuse_status_opt_fbp_r()                                    (0x00820d38U)
 #define fuse_opt_ecc_en_r()                                        (0x00820228U)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mig.h b/drivers/gpu/nvgpu/include/nvgpu/mig.h
index ee6e58e57..4fcaa885c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mig.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mig.h
@@ -124,7 +124,7 @@ struct nvgpu_gpu_instance {
 	 * For Legacy, array is indexed by FBP physical index.
 	 * For MIG, array is indexed by FBP logical index.
 	 */
-	u32 *fbp_rop_l2_en_mask;
+	u32 *fbp_l2_en_mask;
 	/** Memory area to store h/w CE engine ids. */
 	const struct nvgpu_device *lce_devs[NVGPU_MIG_MAX_ENGINES];
 	/* Flag to indicate whether memory partition is supported or not. */
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 59d8d9e9d..1d96199fd 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -734,8 +734,8 @@ static int gk20a_ctrl_get_fbp_l2_masks(
 	int err = 0;
 	const u32 fbp_l2_mask_size = sizeof(u32) *
 			nvgpu_grmgr_get_max_fbps_count(g);
-	u32 *fbp_rop_l2_en_mask =
-		nvgpu_grmgr_get_fbp_rop_l2_en_mask(g, gpu_instance_id);
+	u32 *fbp_l2_en_mask =
+		nvgpu_grmgr_get_fbp_l2_en_mask(g, gpu_instance_id);
 
 	if (args->mask_buf_size > 0) {
 		size_t write_size = fbp_l2_mask_size;
@@ -746,7 +746,7 @@ static int gk20a_ctrl_get_fbp_l2_masks(
 
 		err = copy_to_user((void __user *)(uintptr_t)
 				   args->mask_buf_addr,
-				   fbp_rop_l2_en_mask, write_size);
+				   fbp_l2_en_mask, write_size);
 	}
 
 	if (err == 0)
diff --git a/userspace/units/fuse/nvgpu-fuse-gm20b.c b/userspace/units/fuse/nvgpu-fuse-gm20b.c
index 9e508f480..5879d0aa5 100644
--- a/userspace/units/fuse/nvgpu-fuse-gm20b.c
+++ b/userspace/units/fuse/nvgpu-fuse-gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -209,7 +209,7 @@ int test_fuse_gm20b_basic_fuses(struct unit_module *m,
 					set+i);
 		}
 		for (i = 0; i < GM20B_MAX_FBPS_COUNT; i++) {
-			val = g->ops.fuse.fuse_status_opt_rop_l2_fbp(g, i);
+			val = g->ops.fuse.fuse_status_opt_l2_fbp(g, i);
 			if (val != (set+i)) {
 				unit_err(m,
 					 "%s: ROP_L2_FBP incorrect %u != %u\n",
diff --git a/userspace/units/fuse/nvgpu-fuse-gm20b.h b/userspace/units/fuse/nvgpu-fuse-gm20b.h
index 163b0fed9..b51a7b3ff 100644
--- a/userspace/units/fuse/nvgpu-fuse-gm20b.h
+++ b/userspace/units/fuse/nvgpu-fuse-gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -138,10 +138,10 @@ int test_fuse_gm20b_check_non_sec(struct unit_module *m,
  * Test Type: Feature
  *
  * Targets: gops_fuse.fuse_status_opt_fbio, gops_fuse.fuse_status_opt_fbp,
- *          gops_fuse.fuse_status_opt_rop_l2_fbp, gops_fuse.fuse_status_opt_tpc_gpc,
+ *          gops_fuse.fuse_status_opt_l2_fbp, gops_fuse.fuse_status_opt_tpc_gpc,
  *          gops_fuse.fuse_opt_sec_debug_en, gops_fuse.fuse_opt_priv_sec_en,
  *          gops_fuse.fuse_ctrl_opt_tpc_gpc, gm20b_fuse_status_opt_fbio,
- *          gm20b_fuse_status_opt_fbp, gm20b_fuse_status_opt_rop_l2_fbp,
+ *          gm20b_fuse_status_opt_fbp, gm20b_fuse_status_opt_l2_fbp,
  *          gm20b_fuse_status_opt_tpc_gpc, gm20b_fuse_opt_sec_debug_en,
  *          gm20b_fuse_opt_priv_sec_en, gm20b_fuse_ctrl_opt_tpc_gpc
  *