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gpu: nvgpu: falcon interface update
-Added nvgpu_flcn_mem_scrub_wait() to falcon interface layer to poll imem/dmem scrubbing status complete check for 1msec with status check interval of 10usec. -Called nvgpu_flcn_mem_scrub_wait() in falcon reset interface to check scrubbing status upon falcon/engine reset. -Replaced mem scrubbing wait check code in pmu_enable_hw() by calling nvgpu_flcn_mem_scrub_wait() Bug 200346134 Change-Id: Iac68e24dea466f6dd5facc371947269db64d238d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598644 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -25,6 +25,13 @@
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#include "gk20a/gk20a.h"
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/* Dealy depends on memory size and pwr_clk
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* delay = MAX {IMEM_SIZE, DMEM_SIZE} * 64 + 1) / pwr_clk
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* Timeout set is 1msec & status check at interval 10usec
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*/
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#define MEM_SCRUBBING_TIMEOUT_MAX 1000
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#define MEM_SCRUBBING_TIMEOUT_DEFAULT 10
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int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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@@ -56,15 +63,42 @@ int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn)
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return 0;
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}
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int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn)
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{
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struct nvgpu_timeout timeout;
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int status = 0;
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/* check IMEM/DMEM scrubbing complete status */
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nvgpu_timeout_init(flcn->g, &timeout,
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MEM_SCRUBBING_TIMEOUT_MAX /
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MEM_SCRUBBING_TIMEOUT_DEFAULT,
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NVGPU_TIMER_RETRY_TIMER);
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do {
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if (nvgpu_flcn_get_mem_scrubbing_status(flcn))
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goto exit;
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nvgpu_udelay(MEM_SCRUBBING_TIMEOUT_DEFAULT);
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} while (!nvgpu_timeout_expired(&timeout));
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if (nvgpu_timeout_peek_expired(&timeout))
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status = -ETIMEDOUT;
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exit:
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return status;
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}
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int nvgpu_flcn_reset(struct nvgpu_falcon *flcn)
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{
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int status = -EINVAL;
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int status = 0;
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if (flcn->flcn_ops.reset)
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if (flcn->flcn_ops.reset) {
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status = flcn->flcn_ops.reset(flcn);
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else
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if (!status)
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status = nvgpu_flcn_mem_scrub_wait(flcn);
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} else {
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nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
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flcn->flcn_id);
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status = -EINVAL;
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}
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return status;
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}
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@@ -31,15 +31,11 @@
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#include "gk20a/gk20a.h"
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#define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000
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#define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
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static int nvgpu_pg_init_task(void *arg);
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static int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable)
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{
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struct gk20a *g = pmu->g;
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struct nvgpu_timeout timeout;
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int err = 0;
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nvgpu_log_fn(g, " %s ", g->name);
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@@ -56,29 +52,19 @@ static int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable)
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g->ops.clock_gating.blcg_pmu_load_gating_prod(g,
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g->blcg_enabled);
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/* check for PMU IMEM/DMEM scrubbing complete status */
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nvgpu_timeout_init(g, &timeout,
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PMU_MEM_SCRUBBING_TIMEOUT_MAX /
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PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT,
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NVGPU_TIMER_RETRY_TIMER);
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do {
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if (nvgpu_flcn_get_mem_scrubbing_status(pmu->flcn))
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goto exit;
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nvgpu_udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT);
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} while (!nvgpu_timeout_expired(&timeout));
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if (nvgpu_flcn_mem_scrub_wait(pmu->flcn)) {
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/* keep PMU falcon/engine in reset
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* if IMEM/DMEM scrubbing fails
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*/
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g->ops.pmu.reset_engine(g, false);
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nvgpu_err(g, "Falcon mem scrubbing timeout");
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err = -ETIMEDOUT;
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} else
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}
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} else {
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/* keep PMU falcon/engine in reset */
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g->ops.pmu.reset_engine(g, false);
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}
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exit:
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nvgpu_log_fn(g, "%s Done, status - %d ", g->name, err);
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return err;
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}
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@@ -222,6 +222,7 @@ int nvgpu_flcn_reset(struct nvgpu_falcon *flcn);
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void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable,
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u32 intr_mask, u32 intr_dest);
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bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn);
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int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn);
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bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn);
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bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn);
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int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn,
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