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gpu: nvgpu: multiple address spaces support for subcontexts

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This patch introduces following relationships among various nvgpu
objects to support multiple address spaces with subcontexts.
IOCTLs setting the relationships are shown in the braces.

nvgpu_tsg             1<---->n nvgpu_tsg_subctx (TSG_BIND_CHANNEL_EX)
nvgpu_tsg             1<---->n nvgpu_gr_ctx_mappings (ALLOC_OBJ_CTX)

nvgpu_tsg_subctx      1<---->1 nvgpu_gr_subctx (ALLOC_OBJ_CTX)
nvgpu_tsg_subctx      1<---->n nvgpu_channel (TSG_BIND_CHANNEL_EX)

nvgpu_gr_ctx_mappings 1<---->n nvgpu_gr_subctx (ALLOC_OBJ_CTX)
nvgpu_gr_ctx_mappings 1<---->1 vm_gk20a (ALLOC_OBJ_CTX)

On unbinding the channel, objects are deleted according
to dependencies.

Without subcontexts, gr_ctx buffers mappings are maintained in the
struct nvgpu_gr_ctx. For subcontexts, they are maintained in the
struct nvgpu_gr_subctx.

Preemption buffer with index NVGPU_GR_CTX_PREEMPT_CTXSW and PM
buffer with index NVGPU_GR_CTX_PM_CTX are to be mapped in all
subcontexts when they are programmed from respective ioctls.

Global GR context buffers are to be programmed only for VEID0.
Based on the channel object class the state is patched in
the patch buffer in every ALLOC_OBJ_CTX call unlike
setting it for only first channel like before.

PM and preemptions buffers programming is protected under TSG
ctx_init_lock.

tsg->vm is now removed. VM reference for gr_ctx buffers mappings
is managed through gr_ctx or gr_subctx mappings object.

For vGPU, gr_subctx and mappings objects are created to reference
VMs for the gr_ctx lifetime.

The functions nvgpu_tsg_subctx_alloc_gr_subctx and nvgpu_tsg_-
subctx_setup_subctx_header sets up the subcontext struct header
for native driver.

The function nvgpu_tsg_subctx_alloc_gr_subctx is called from
vgpu to manage the gr ctx mapping references.

free_subctx is now done when unbinding channel considering
references to the subcontext by other channels. It will unmap
the buffers in native driver case. It will just release the
VM reference in vgpu case.

Note that TEGRA_VGPU_CMD_FREE_CTX_HEADER ioctl is not called
by vgpu any longer as it would be taken care by native driver.

Bug 3677982

Change-Id: Ia439b251ff452a49f8514498832e24d04db86d2f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2718760
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sagar Kamble
2022-05-18 17:32:18 +05:30
committed by mobile promotions
parent 9e13b61d4e
commit f55fd5dc8c
37 changed files with 1963 additions and 404 deletions
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40
userspace/units/gr/ctx/nvgpu-gr-ctx.c
View File

@@ -42,6 +42,8 @@
#include "../nvgpu-gr.h"
#include "nvgpu-gr-ctx.h"
#include "../../fifo/nvgpu-fifo-common.h"
#define DUMMY_SIZE 0xF0U
static u64 nvgpu_gmmu_map_locked_stub(struct vm_gk20a *vm,
@@ -92,14 +94,24 @@ int test_gr_ctx_error_injection(struct unit_module *m,
u64 low_hole = SZ_4K * 16UL;
struct nvgpu_channel *channel = (struct nvgpu_channel *)
malloc(sizeof(struct nvgpu_channel));
struct nvgpu_tsg *tsg = (struct nvgpu_tsg *)
malloc(sizeof(struct nvgpu_tsg));
struct nvgpu_tsg *tsg;
u32 i;
if (channel == NULL || tsg == NULL) {
if (channel == NULL) {
unit_return_fail(m, "failed to allocate channel/tsg");
}
err = test_fifo_init_support(m, g, NULL);
if (err != 0) {
unit_return_fail(m, "failed to init fifo support\n");
return err;
}
tsg = nvgpu_tsg_open(g, 0);
if (!tsg) {
unit_return_fail(m, "failed to allocate tsg");
}
desc = nvgpu_gr_ctx_desc_alloc(g);
if (!desc) {
unit_return_fail(m, "failed to allocate memory");
@@ -147,7 +159,7 @@ int test_gr_ctx_error_injection(struct unit_module *m,
tsg->gr_ctx = gr_ctx;
mappings = nvgpu_gr_ctx_alloc_or_get_mappings(g, tsg, vm);
mappings = nvgpu_gr_ctx_alloc_or_get_mappings(g, tsg, channel);
if (mappings == NULL) {
unit_return_fail(m, "failed to allocate gr_ctx mappings");
}
@@ -179,7 +191,7 @@ int test_gr_ctx_error_injection(struct unit_module *m,
/* Inject kmem alloc failures to trigger mapping failures */
for (i = 0; i < 2; i++) {
nvgpu_posix_enable_fault_injection(kmem_fi, true, 2 * i);
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx,
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, NULL,
global_desc, mappings, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -188,8 +200,8 @@ int test_gr_ctx_error_injection(struct unit_module *m,
}
/* global ctx_desc size is not set. */
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, global_desc,
mappings, false);
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, NULL,
global_desc, mappings, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
@@ -211,8 +223,8 @@ int test_gr_ctx_error_injection(struct unit_module *m,
/* Fail global ctx buffer mappings */
for (i = 0; i < 4; i++) {
nvgpu_posix_enable_fault_injection(kmem_fi, true, 4 + (2 * i));
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, global_desc,
mappings, false);
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, NULL,
global_desc, mappings, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
@@ -221,8 +233,8 @@ int test_gr_ctx_error_injection(struct unit_module *m,
/* Successful mapping */
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, global_desc,
mappings, false);
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, NULL,
global_desc, mappings, false);
if (err != 0) {
unit_return_fail(m, "failed to map global buffers");
}
@@ -253,6 +265,12 @@ int test_gr_ctx_error_injection(struct unit_module *m,
nvgpu_gr_ctx_desc_free(g, desc);
nvgpu_vm_put(g->mm.bar1.vm);
err = test_fifo_remove_support(m, g, NULL);
if (err != 0) {
unit_return_fail(m, "failed to remove fifo support\n");
return err;
}
return UNIT_SUCCESS;
}