gpu: nvgpu: initialize masks for the perfmon counters 3

Initialize the perfmon counters #3 masks to be same values as ELPG.
Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030,
but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0.

Bug 2833620

Change-Id: I3a424345aec6176a97dd20fb2c68a6e2faf955ad
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299
(cherry picked from commit bbef4c6927)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2351905
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>

drivers/gpu/nvgpu/gk20a/pmu_gk20a.c

@@ -760,6 +760,10 @@ void gk20a_pmu_init_perfmon_counter(struct gk20a *g)
 		pwr_pmu_idle_mask_gr_enabled_f() |
 		pwr_pmu_idle_mask_ce_2_enabled_f());
 
+	/* assign same mask setting from GR ELPG to counter #3 */
+	data = gk20a_readl(g, pwr_pmu_idle_mask_1_supp_r(0));
+	gk20a_writel(g, pwr_pmu_idle_mask_1_r(3), data);
+
 	/* disable idle filtering for counters 3 and 6 */
 	data = gk20a_readl(g, pwr_pmu_idle_ctrl_r(3));
 	data = set_field(data, pwr_pmu_idle_ctrl_value_m() |

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -720,7 +720,7 @@ static const struct gpu_ops gv11b_ops = {
 		.pmu_mutex_release = gk20a_pmu_mutex_release,
 		.pmu_is_interrupted = gk20a_pmu_is_interrupted,
 		.pmu_isr = gk20a_pmu_isr,
-		.pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
+		.pmu_init_perfmon_counter = gv11b_pmu_init_perfmon_counter,
 		.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,
 		.pmu_read_idle_counter = gk20a_pmu_read_idle_counter,
 		.pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter,

drivers/gpu/nvgpu/gv11b/pmu_gv11b.c

@@ -30,6 +30,7 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
 
+#include "gk20a/pmu_gk20a.h"
 #include "gp10b/pmu_gp10b.h"
 #include "gp106/pmu_gp106.h"
 
@@ -440,6 +441,17 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg,
 							msg->msg.pg.msg_type);
 }
 
+void gv11b_pmu_init_perfmon_counter(struct gk20a *g)
+{
+	u32 data;
+
+	gk20a_pmu_init_perfmon_counter(g);
+
+	/* assign same mask setting from GR ELPG to counter #3 */
+	data = gk20a_readl(g, pwr_pmu_idle_mask_2_supp_r(0));
+        gk20a_writel(g, pwr_pmu_idle_mask_2_r(3), data);
+}
+
 int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
 {
 	struct nvgpu_pmu *pmu = &g->pmu;

drivers/gpu/nvgpu/gv11b/pmu_gv11b.h

@@ -29,6 +29,7 @@ struct gk20a;
 
 bool gv11b_is_pmu_supported(struct gk20a *g);
 int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu);
+void gv11b_pmu_init_perfmon_counter(struct gk20a *g);
 int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
 int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id);
 bool gv11b_is_lazy_bootstrap(u32 falcon_id);