nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu:nvgpu:gm20b: disable irqs when hs pmu executes

Browse Source 
bug 200040021

polling halt irq to check for hs bin completion
keep irqs disabled to avoid executing irq handler

Change-Id: Ic245d89580444dcbf1cf5ec34bfe0f8b0c5bbc0f
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/554659
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Vijayakumar
2014-10-08 20:07:37 +05:30
committed by Dan Willemsen
parent b318d4c407
commit f56d50ddac
4 changed files with 45 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
View File

@@ -1048,7 +1048,7 @@ static int pmu_idle(struct pmu_gk20a *pmu)
return 0; return 0;
} }
static void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable) void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable)
{ {
struct gk20a *g = gk20a_from_pmu(pmu); struct gk20a *g = gk20a_from_pmu(pmu);

2
drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
View File

@@ -1145,5 +1145,5 @@ int gk20a_pmu_ap_send_command(struct gk20a *g,
union pmu_ap_cmd *p_ap_cmd, bool b_block); union pmu_ap_cmd *p_ap_cmd, bool b_block);
int gk20a_aelpg_init(struct gk20a *g); int gk20a_aelpg_init(struct gk20a *g);
int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id); int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable);
#endif /*__PMU_GK20A_H__*/ #endif /*__PMU_GK20A_H__*/

47
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -63,6 +63,11 @@ get_ucode_details pmu_acr_supp_ucode_list[] = {
/*Once is LS mode, cpuctl_alias is only accessible*/ /*Once is LS mode, cpuctl_alias is only accessible*/
void start_gm20b_pmu(struct gk20a *g) void start_gm20b_pmu(struct gk20a *g)
{ {
/*disable irqs for hs falcon booting as we will poll for halt*/
mutex_lock(&g->pmu.isr_mutex);
pmu_enable_irq(&g->pmu, true);
g->pmu.isr_enabled = true;
mutex_unlock(&g->pmu.isr_mutex);
gk20a_writel(g, pwr_falcon_cpuctl_alias_r(), gk20a_writel(g, pwr_falcon_cpuctl_alias_r(),
pwr_falcon_cpuctl_startcpu_f(1)); pwr_falcon_cpuctl_startcpu_f(1));
} }
@@ -1116,6 +1121,11 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, struct flcn_bl_dmem_desc *desc,
pmu_copy_to_dmem(pmu, g->acr.pmu_args, pmu_copy_to_dmem(pmu, g->acr.pmu_args,
(u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
/*disable irqs for hs falcon booting as we will poll for halt*/
mutex_lock(&pmu->isr_mutex);
pmu_enable_irq(pmu, false);
pmu->isr_enabled = false;
mutex_unlock(&pmu->isr_mutex);
err = bl_bootstrap(pmu, desc, bl_sz); err = bl_bootstrap(pmu, desc, bl_sz);
if (err) if (err)
return err; return err;
@@ -1216,8 +1226,9 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt)
* to PMU halt * to PMU halt
*/ */
gk20a_writel(g, pwr_falcon_irqsclr_r(), if (clear_halt_interrupt_status(g, GPU_TIMEOUT_DEFAULT))
gk20a_readl(g, pwr_falcon_irqsclr_r()) & (~(0x10))); goto err_unmap_bl;
gm20b_dbg_pmu("err reg :%x\n", readl(mc + gm20b_dbg_pmu("err reg :%x\n", readl(mc +
MC_ERR_GENERALIZED_CARVEOUT_STATUS_0)); MC_ERR_GENERALIZED_CARVEOUT_STATUS_0));
gm20b_dbg_pmu("phys sec reg %x\n", gk20a_readl(g, gm20b_dbg_pmu("phys sec reg %x\n", gk20a_readl(g,
@@ -1228,10 +1239,11 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt)
/* Poll for HALT */ /* Poll for HALT */
if (b_wait_for_halt) { if (b_wait_for_halt) {
err = pmu_wait_for_halt(g, GPU_TIMEOUT_DEFAULT); err = pmu_wait_for_halt(g, GPU_TIMEOUT_DEFAULT);
if (err == 0) if (err == 0) {
/* Clear the HALT interrupt */ /* Clear the HALT interrupt */
gk20a_writel(g, pwr_falcon_irqsclr_r(), if (clear_halt_interrupt_status(g, GPU_TIMEOUT_DEFAULT))
gk20a_readl(g, pwr_falcon_irqsclr_r()) & (~(0x10))); goto err_unmap_bl;
}
else else
goto err_unmap_bl; goto err_unmap_bl;
} }
@@ -1281,3 +1293,28 @@ int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout)
return -EBUSY; return -EBUSY;
return 0; return 0;
} }
/*!
* Wait for PMU halt interrupt status to be cleared
* @param[in] g GPU object pointer
* @param[in] timeout_us Timeout in Us for PMU to halt
* @return '0' if PMU halt irq status is clear
*/
int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout)
{
u32 data = 0;
while (timeout != 0) {
gk20a_writel(g, pwr_falcon_irqsclr_r(),
gk20a_readl(g, pwr_falcon_irqsclr_r()) | (0x10));
data = gk20a_readl(g, (pwr_falcon_irqstat_r()));
if ((data & pwr_falcon_irqstat_halt_true_f()) !=
pwr_falcon_irqstat_halt_true_f())
/*halt irq is clear*/
break;
timeout--;
udelay(1);
}
if (timeout == 0)
return -EBUSY;
return 0;
}

1
drivers/gpu/nvgpu/gm20b/acr_gm20b.h
View File

@@ -383,4 +383,5 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g);
int gm20b_pmu_setup_sw(struct gk20a *g); int gm20b_pmu_setup_sw(struct gk20a *g);
int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt);
int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_us); int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_us);
int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
#endif /*__ACR_GM20B_H_*/ #endif /*__ACR_GM20B_H_*/