diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
index d3dd23aa5..de6e12e7f 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
@@ -224,8 +224,8 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
 		ALIGN(gpccs->code.offset, 256U);
 	p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256U);
 	p_img->data = (u32 *)
-		((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon) +
-					gpccs->boot.offset);
+	(void *)((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon)
+				+ gpccs->boot.offset);
 	p_img->data_size = ALIGN(p_img->desc->image_size, 256U);
 	p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
 
@@ -488,7 +488,7 @@ static int lsfm_discover_and_add_sub_wprs(struct gk20a *g,
 	u32 sub_wpr_index;
 
 	for (sub_wpr_index = 1;
-		sub_wpr_index <= LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX;
+		sub_wpr_index <= (u32) LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX;
 		sub_wpr_index++) {
 
 		switch (sub_wpr_index) {
@@ -858,7 +858,7 @@ static int lsfm_init_wpr_contents(struct gk20a *g,
 	/* Tag the terminator WPR header with an invalid falcon ID. */
 	last_wpr_hdr.falcon_id = FALCON_ID_INVALID;
 	tmp = nvgpu_safe_mult_u32(plsfm->managed_flcn_cnt,
-					sizeof(struct lsf_wpr_header_v1));
+					(u32)sizeof(struct lsf_wpr_header_v1));
 	nvgpu_assert(tmp <= U32_MAX);
 	nvgpu_mem_wr_n(g, ucode, (u32)tmp, &last_wpr_hdr,
 		(u32)sizeof(struct lsf_wpr_header_v1));
diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h
index 579392f91..c704ded5d 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h
+++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h
@@ -222,8 +222,9 @@ struct ls_flcn_mgr_v1 {
 };
 
 int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g);
-
+#ifdef CONFIG_NVGPU_LS_PMU
 int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
+#endif
 int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
 int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
 #ifdef CONFIG_NVGPU_DGPU
diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
index 8f255f614..ac7c64f2c 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
@@ -207,8 +207,7 @@ static int acr_hs_bl_exec(struct gk20a *g, struct nvgpu_acr *acr,
 	/* Fill HS BL info */
 	bl_info.bl_src = hs_bl->hs_bl_ucode.cpu_va;
 	bl_info.bl_desc = acr_desc->ptr_bl_dmem_desc;
-	nvgpu_assert(acr_desc->bl_dmem_desc_size <= U32_MAX);
-	bl_info.bl_desc_size = (u32)acr_desc->bl_dmem_desc_size;
+	bl_info.bl_desc_size = acr_desc->bl_dmem_desc_size;
 	nvgpu_assert(hs_bl->hs_bl_ucode.size <= U32_MAX);
 	bl_info.bl_size = (u32)hs_bl->hs_bl_ucode.size;
 	bl_info.bl_start_tag = hs_bl->hs_bl_desc->bl_start_tag;
diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c b/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c
index 5da1eba1f..2bc9b5cd6 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c
@@ -56,22 +56,22 @@ static void gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
 	if (is_recovery) {
 		acr_desc->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0U;
 	} else {
-		acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
-		acr_fw_hdr = (struct acr_fw_header *)
+		acr_fw_bin_hdr = (struct bin_hdr *)(void *)acr_fw->data;
+		acr_fw_hdr = (struct acr_fw_header *)(void *)
 			(acr_fw->data + acr_fw_bin_hdr->header_offset);
 
-		acr_ucode_data = (u32 *)(acr_fw->data +
+		acr_ucode_data = (u32 *)(void *)(acr_fw->data +
 			acr_fw_bin_hdr->data_offset);
-		acr_ucode_header = (u32 *)(acr_fw->data +
+		acr_ucode_header = (u32 *)(void *)(acr_fw->data +
 			acr_fw_hdr->hdr_offset);
 
 		/* During recovery need to update blob size as 0x0*/
-		acr_desc->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)
+		acr_desc->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)(void *)
 			((u8 *)(acr_desc->acr_ucode.cpu_va) +
 			acr_ucode_header[2U]);
 
 		/* Patch WPR info to ucode */
-		acr_dmem_desc = (struct flcn_acr_desc_v1 *)
+		acr_dmem_desc = (struct flcn_acr_desc_v1 *)(void *)
 			&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
 
 		acr_dmem_desc->nonwpr_ucode_blob_start =
@@ -190,28 +190,28 @@ static u32 gv11b_acr_lsf_conifg(struct gk20a *g,
 	return lsf_enable_mask;
 }
 
-static void gv11b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
+static void gv11b_acr_default_sw_init(struct gk20a *g, struct hs_acr *acr_desc)
 {
-	struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
+	struct hs_flcn_bl *hs_bl = &acr_desc->acr_hs_bl;
 
 	nvgpu_log_fn(g, " ");
 
 	hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
 
-	hs_acr->acr_type = ACR_DEFAULT;
-	hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
+	acr_desc->acr_type = ACR_DEFAULT;
+	acr_desc->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
 
-	hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1;
-	hs_acr->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
+	acr_desc->ptr_bl_dmem_desc = &acr_desc->bl_dmem_desc_v1;
+	acr_desc->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
 
-	hs_acr->acr_flcn = g->pmu->flcn;
-	hs_acr->acr_flcn_setup_boot_config =
+	acr_desc->acr_flcn = g->pmu->flcn;
+	acr_desc->acr_flcn_setup_boot_config =
 		g->ops.pmu.flcn_setup_boot_config;
-	hs_acr->report_acr_engine_bus_err_status =
+	acr_desc->report_acr_engine_bus_err_status =
 		nvgpu_pmu_report_bar0_pri_err_status;
-	hs_acr->acr_engine_bus_err_status =
+	acr_desc->acr_engine_bus_err_status =
 		g->ops.pmu.bar0_error_status;;
-	hs_acr->acr_validate_mem_integrity = g->ops.pmu.validate_mem_integrity;
+	acr_desc->acr_validate_mem_integrity = g->ops.pmu.validate_mem_integrity;
 }
 
 void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.h b/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.h
index f6dd0df3e..ad96d779f 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.h
+++ b/drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.h
@@ -25,6 +25,7 @@
 
 struct gk20a;
 struct nvgpu_acr;
+struct hs_acr;
 
 void gv11b_acr_fill_bl_dmem_desc(struct gk20a *g, struct nvgpu_acr *acr,
 	struct hs_acr *acr_desc, u32 *acr_ucode_header);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr.h
index 4bc5fdf64..322f60975 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/acr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr.h
@@ -32,14 +32,13 @@ int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr);
 #ifdef CONFIG_NVGPU_DGPU
 int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr,
 	size_t size);
+int nvgpu_acr_self_hs_load_bootstrap(struct gk20a *g, struct nvgpu_falcon *flcn,
+	struct nvgpu_firmware *hs_fw, u32 timeout);
 #endif
 int nvgpu_acr_construct_execute(struct gk20a *g, struct nvgpu_acr *acr);
 int nvgpu_acr_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr);
 bool nvgpu_acr_is_lsf_lazy_bootstrap(struct gk20a *g, struct nvgpu_acr *acr,
 	u32 falcon_id);
 
-int nvgpu_acr_self_hs_load_bootstrap(struct gk20a *g, struct nvgpu_falcon *flcn,
-	struct nvgpu_firmware *hs_fw, u32 timeout);
-
 #endif /* NVGPU_ACR_H */