From f5acc98db3c8650a1b18581a650cd838c4cddea9 Mon Sep 17 00:00:00 2001 From: rmylavarapu Date: Tue, 17 Mar 2020 16:51:09 +0530 Subject: [PATCH] gpu: nvgpu: Refactor Super surface lite unit - Changed the names of structs as per private/public naming convention. - Removed unwanted code in struct super_surface. NVGPU-4486 Change-Id: I5834c2296ccbe1545bca6a608ad88817a9104fb8 Signed-off-by: rmylavarapu Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313989 Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mahantesh Kumbar Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- .../common/pmu/super_surface/super_surface.c | 34 +++++++++---------- .../pmu/super_surface/super_surface_priv.h | 32 ++++++----------- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 4 +-- drivers/gpu/nvgpu/include/nvgpu/pmu/fw.h | 4 +-- .../nvgpu/include/nvgpu/pmu/super_surface.h | 20 +++++------ 5 files changed, 41 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface.c b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface.c index 3f6b53fbe..27ff7330d 100644 --- a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface.c +++ b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,7 +28,7 @@ #include "super_surface_priv.h" int nvgpu_pmu_super_surface_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu, - struct pmu_super_surface *ss) + struct nvgpu_pmu_super_surface *ss) { struct vm_gk20a *vm = g->mm.pmu.vm; int err = 0; @@ -39,7 +39,7 @@ int nvgpu_pmu_super_surface_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu, return 0; } - err = nvgpu_dma_alloc_map(vm, sizeof(struct nv_pmu_super_surface), + err = nvgpu_dma_alloc_map(vm, sizeof(struct super_surface), &ss->super_surface_buf); if (err != 0) { nvgpu_err(g, "failed to allocate pmu suffer surface\n"); @@ -49,7 +49,7 @@ int nvgpu_pmu_super_surface_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu, } struct nvgpu_mem *nvgpu_pmu_super_surface_mem(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss) + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss) { return &ss->super_surface_buf; } @@ -62,11 +62,11 @@ struct nvgpu_mem *nvgpu_pmu_super_surface_mem(struct gk20a *g, * GET_STATUS ID_TYPE. */ void nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss) + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss) { - struct nv_pmu_super_surface_member_descriptor ssmd; + struct super_surface_member_descriptor ssmd; u32 ssmd_size = (u32) - sizeof(struct nv_pmu_super_surface_member_descriptor); + sizeof(struct super_surface_member_descriptor); u32 idx = 0U; nvgpu_log_fn(g, " "); @@ -140,28 +140,28 @@ u32 nvgpu_pmu_get_ss_member_get_status_size(struct gk20a *g, } u32 nvgpu_pmu_get_ss_cmd_fbq_offset(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss, u32 id) + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss, u32 id) { - return (u32)offsetof(struct nv_pmu_super_surface, + return (u32)offsetof(struct super_surface, fbq.cmd_queues.queue[id]); } u32 nvgpu_pmu_get_ss_msg_fbq_offset(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss) + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss) { - return (u32)offsetof(struct nv_pmu_super_surface, + return (u32)offsetof(struct super_surface, fbq.msg_queue); } u32 nvgpu_pmu_get_ss_msg_fbq_element_offset(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss, u32 idx) + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss, u32 idx) { - return (u32)offsetof(struct nv_pmu_super_surface, + return (u32)offsetof(struct super_surface, fbq.msg_queue.element[idx]); } void nvgpu_pmu_super_surface_deinit(struct gk20a *g, struct nvgpu_pmu *pmu, - struct pmu_super_surface *ss) + struct nvgpu_pmu_super_surface *ss) { nvgpu_log_fn(g, " "); @@ -177,10 +177,10 @@ void nvgpu_pmu_super_surface_deinit(struct gk20a *g, struct nvgpu_pmu *pmu, } int nvgpu_pmu_super_surface_init(struct gk20a *g, struct nvgpu_pmu *pmu, - struct pmu_super_surface **super_surface) + struct nvgpu_pmu_super_surface **super_surface) { - *super_surface = (struct pmu_super_surface *) nvgpu_kzalloc(g, - sizeof(struct pmu_super_surface)); + *super_surface = (struct nvgpu_pmu_super_surface *) nvgpu_kzalloc(g, + sizeof(struct nvgpu_pmu_super_surface)); if (*super_surface == NULL) { return -ENOMEM; } diff --git a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h index 4f2ffe38a..832685aaa 100644 --- a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h +++ b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h @@ -56,7 +56,7 @@ struct nvgpu_mem; #define NV_RM_PMU_SUPER_SURFACE_MEMBER_ID_TYPE_GET_STATUS BIT(17) #define NV_RM_PMU_SUPER_SURFACE_MEMBER_ID_RSVD (0x00UL << 20U) -struct nv_pmu_super_surface_member_descriptor { +struct super_surface_member_descriptor { /* The member ID (@see NV_PMU_SUPER_SURFACE_MEMBER_ID_). */ u32 id; @@ -71,21 +71,20 @@ struct nv_pmu_super_surface_member_descriptor { }; /* PMU super surface */ -struct nv_pmu_super_surface_hdr { +struct super_surface_hdr { struct falc_u64 address; u32 member_mask; u16 dmem_buffer_size_max; }; -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_super_surface_hdr, - sizeof(struct nv_pmu_super_surface_hdr)); +NV_PMU_MAKE_ALIGNED_STRUCT(super_surface_hdr, sizeof(struct super_surface_hdr)); /* * Global Super Surface structure for combined INIT data required by PMU. * NOTE: Any new substructures or entries must be aligned. */ -struct nv_pmu_super_surface { - struct nv_pmu_super_surface_member_descriptor +struct super_surface { + struct super_surface_member_descriptor ssmd[NV_PMU_SUPER_SURFACE_MEMBER_DESCRIPTOR_COUNT]; struct { @@ -93,31 +92,20 @@ struct nv_pmu_super_surface { struct nv_pmu_fbq_msg_queue msg_queue; } fbq; - union nv_pmu_super_surface_hdr_aligned hdr; + union super_surface_hdr_aligned hdr; - union { - u8 ss_unmapped_members_rsvd[SS_UNMAPPED_MEMBERS_SIZE]; - - /* - * Below members are only for reference to know - * supported boardobjs from nvgpu, should not be - * accessed any boardobj member from below list - * in nvgpu using these members, instead use ssmd - * member present above to know the offset of - * required boardobj from super surface in nvgpu - */ - }; + u8 ss_unmapped_members_rsvd[SS_UNMAPPED_MEMBERS_SIZE]; }; /* nvgpu super surface */ -struct pmu_super_surface { +struct nvgpu_pmu_super_surface { /* super surface members */ struct nvgpu_mem super_surface_buf; - struct nv_pmu_super_surface_member_descriptor + struct super_surface_member_descriptor ssmd_set[NV_PMU_SUPER_SURFACE_MEMBER_DESCRIPTOR_COUNT]; - struct nv_pmu_super_surface_member_descriptor + struct super_surface_member_descriptor ssmd_get_status[NV_PMU_SUPER_SURFACE_MEMBER_DESCRIPTOR_COUNT]; }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 55b600a2d..49f0ceae7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -40,7 +40,7 @@ struct pmu_sequences; struct pmu_mutexes; struct nvgpu_pmu_lsfm; -struct pmu_super_surface; +struct nvgpu_pmu_super_surface; struct nvgpu_pmu_pg; struct nvgpu_pmu_perfmon; struct nvgpu_clk_pmupstate; @@ -298,7 +298,7 @@ struct nvgpu_pmu { struct pmu_mutexes *mutexes; struct nvgpu_pmu_lsfm *lsfm; - struct pmu_super_surface *super_surface; + struct nvgpu_pmu_super_surface *super_surface; struct nvgpu_pmu_pg *pg; struct nvgpu_pmu_perfmon *pmu_perfmon; struct nvgpu_clk_pmupstate *clk_pmu; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/fw.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/fw.h index 2939af881..109d51814 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/fw.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/fw.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,7 +29,7 @@ struct nvgpu_pmu; struct pmu_sequence; -struct pmu_super_surface; +struct nvgpu_pmu_super_surface; struct pmu_pg_cmd; struct boardobjgrp; struct boardobjgrp_pmu_cmd; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/super_surface.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/super_surface.h index a048f48c2..6e7d3b138 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/super_surface.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/super_surface.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,7 +27,7 @@ struct nvgpu_mem; struct nvgpu_pmu; -struct pmu_super_surface; +struct nvgpu_pmu_super_surface; /* * Super surface member BIT identification used in member_mask indicating @@ -64,23 +64,23 @@ u32 nvgpu_pmu_get_ss_member_get_status_offset(struct gk20a *g, u32 nvgpu_pmu_get_ss_member_get_status_size(struct gk20a *g, struct nvgpu_pmu *pmu, u32 member_id); void nvgpu_pmu_ss_create_ssmd_lookup_table(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss); + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss); struct nvgpu_mem *nvgpu_pmu_super_surface_mem(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss); + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss); int nvgpu_pmu_super_surface_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu, - struct pmu_super_surface *ss); + struct nvgpu_pmu_super_surface *ss); u32 nvgpu_pmu_get_ss_cmd_fbq_offset(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss, u32 id); + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss, u32 id); u32 nvgpu_pmu_get_ss_msg_fbq_offset(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss); + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss); u32 nvgpu_pmu_get_ss_msg_fbq_element_offset(struct gk20a *g, - struct nvgpu_pmu *pmu, struct pmu_super_surface *ss, u32 idx); + struct nvgpu_pmu *pmu, struct nvgpu_pmu_super_surface *ss, u32 idx); void nvgpu_pmu_super_surface_deinit(struct gk20a *g, struct nvgpu_pmu *pmu, - struct pmu_super_surface *ss); + struct nvgpu_pmu_super_surface *ss); int nvgpu_pmu_super_surface_init(struct gk20a *g, struct nvgpu_pmu *pmu, - struct pmu_super_surface **super_suface); + struct nvgpu_pmu_super_surface **super_suface); #endif /* SUPER_SURFACE_H */