gpu: nvgpu: Change quantize order in GPCPLL NA mode

When calculating fractional divider in GPCPLL NA mode quantize voltage
before (used to do it after) applying DFS_COEFF, to follow h/w order.

Bug 1555318

Change-Id: I37be2bc73cd1f849695b94acc4ff21caf26e8b97
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/552741
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
This commit is contained in:
Alex Frid
2014-10-01 16:24:58 -07:00
committed by Dan Willemsen
parent 2d0bcfa331
commit f65d2dde97

View File

@@ -302,10 +302,11 @@ static void clk_config_dvfs_ndiv(int mv, u32 n_eff, struct na_dvfs *d)
u32 rem, rem_range; u32 rem, rem_range;
struct pll_parms *p = &gpc_pll_params; struct pll_parms *p = &gpc_pll_params;
det_delta = (mv * 1000 - d->uv_cal); det_delta = DIV_ROUND_CLOSEST(mv * 1000 - p->uvdet_offs,
det_delta = min(det_delta, d->dfs_det_max * p->uvdet_slope); p->uvdet_slope);
det_delta -= d->dfs_ext_cal;
det_delta = min(det_delta, d->dfs_det_max);
det_delta = det_delta * d->dfs_coeff; det_delta = det_delta * d->dfs_coeff;
det_delta = DIV_ROUND_CLOSEST(det_delta, p->uvdet_slope);
n = (int)(n_eff << DFS_DET_RANGE) - det_delta; n = (int)(n_eff << DFS_DET_RANGE) - det_delta;
BUG_ON((n < 0) || (n > (p->max_N << DFS_DET_RANGE))); BUG_ON((n < 0) || (n > (p->max_N << DFS_DET_RANGE)));