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gpu: nvgpu: move fifo intr to hal/fifo

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Removed intr_0_error_mask ops

Added below ops for fifo intr
intr_0_enable
intr_1_enable
intr_0_isr
intr_1_isr

JIRA NVGPU-1310

Change-Id: I19bd1a380a89cffd582d6c4a0b7796a46fec5afb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072144
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-12 16:21:08 -07:00
committed by mobile promotions
parent 217be5e492
commit f66f3e1341
21 changed files with 855 additions and 540 deletions
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2
drivers/gpu/nvgpu/include/nvgpu/fifo.h
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@@ -35,6 +35,8 @@
#define RC_TYPE_FORCE_RESET 7U
#define RC_TYPE_SCHED_ERR 8U
#define INVAL_ID (~U32(0U))
struct gk20a;
struct nvgpu_channel_hw_state {