From f6706874417f94d3fd1f0bf7e931240ec87cad01 Mon Sep 17 00:00:00 2001 From: Antony Clince Alex Date: Wed, 23 Mar 2022 01:56:27 +0000 Subject: [PATCH] gpu: nvgpu: move ltc_tstg_mgmt register setup The ltc_ltcs_ltss_tstg_set_mgmt_3 register should only be configured after ACR init, hence move it down the init order from early_init to finalize_poweron after acr is loaded. Bug 3514215 Change-Id: I2462715d25f75b7476ab163cd6c9f73ced5efb6d Signed-off-by: Antony Clince Alex Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2685547 Reviewed-by: svcacv Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Mahantesh Kumbar Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 9 +++++++++ drivers/gpu/nvgpu/common/ltc/ltc.c | 4 ---- drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h | 4 ++-- drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c | 6 ++++-- drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h | 2 +- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 7c9692332..55d2d55a9 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -900,6 +900,15 @@ int nvgpu_finalize_poweron(struct gk20a *g) NVGPU_INIT_TABLE_ENTRY(&nvgpu_gr_enable_hw, NO_FLAG), NVGPU_INIT_TABLE_ENTRY(g->ops.acr.acr_construct_execute, NVGPU_SEC_PRIVSECURITY), + /** + * Set ltc_lts_set_mgmt registers only after ACR boot(See + * bug200601972 for details). In order to accomplish this + * ltc_lts_set_mgmt_setup is decoupled from + * nvgpu_init_ltc_support which needs to be executed before ACR + * boot. + */ + NVGPU_INIT_TABLE_ENTRY(g->ops.ltc.ltc_lts_set_mgmt_setup, + NO_FLAG), /** * Set atomic mode after acr boot(See Bug 3268664 for * details). For acr to boot, nvgpu_init_fb_support diff --git a/drivers/gpu/nvgpu/common/ltc/ltc.c b/drivers/gpu/nvgpu/common/ltc/ltc.c index ed81d49e1..b37a9d1f9 100644 --- a/drivers/gpu/nvgpu/common/ltc/ltc.c +++ b/drivers/gpu/nvgpu/common/ltc/ltc.c @@ -74,10 +74,6 @@ int nvgpu_init_ltc_support(struct gk20a *g) } } - if (g->ops.ltc.ltc_lts_set_mgmt_setup != NULL) { - g->ops.ltc.ltc_lts_set_mgmt_setup(g); - } - if (g->ops.ltc.intr.configure != NULL) { nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_LTC, NVGPU_CIC_INTR_ENABLE); diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h index b176667cf..3612d1813 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -38,7 +38,7 @@ void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index); #endif void ga10b_ltc_init_fs_state(struct gk20a *g); -void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g); +int ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g); u64 ga10b_determine_L2_size_bytes(struct gk20a *g); int ga10b_lts_ecc_init(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c index 3ff4fbfb5..444cca105 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -75,7 +75,7 @@ void ga10b_ltc_init_fs_state(struct gk20a *g) nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r(), reg); } -void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g) +int ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g) { u32 reg; @@ -89,6 +89,8 @@ void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g) ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_enabled_f()); nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_3_r(), reg); } + + return 0; } #ifdef CONFIG_NVGPU_DEBUGGER diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h index 8ad49bb26..9665409c1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h @@ -415,7 +415,7 @@ struct gops_ltc { #if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) void (*set_enabled)(struct gk20a *g, bool enabled); #endif - void (*ltc_lts_set_mgmt_setup)(struct gk20a *g); + int (*ltc_lts_set_mgmt_setup)(struct gk20a *g); #ifdef CONFIG_NVGPU_GRAPHICS void (*set_zbc_color_entry)(struct gk20a *g, u32 *color_val_l2, u32 index);