From f6a2b839cfa5660fd4df2b01c9267563f94f54ac Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 5 Dec 2018 13:35:37 -0500 Subject: [PATCH] gpu: nvgpu: make PMU_CMD_FLAGS* U8 values These macros are for setting the 8 bit ctrl_flags member of the pmu_hdr struct. Making these macros U8 fixes MISRA 10.3 violations for implicit assignment of different types. JIRA NVGPU-1008 Change-Id: I325c845b01aa044d08458b51409b04ef29699335 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1966339 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h index 45e8c6ff0..3fcfc7e5d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h +++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h @@ -109,10 +109,10 @@ typedef u8 flcn_status; #define PMU_CMD_FLAGS_PMU_MASK (0xF0) -#define PMU_CMD_FLAGS_STATUS BIT(0) -#define PMU_CMD_FLAGS_INTR BIT(1) -#define PMU_CMD_FLAGS_EVENT BIT(2) -#define PMU_CMD_FLAGS_WATERMARK BIT(3) +#define PMU_CMD_FLAGS_STATUS BIT8(0) +#define PMU_CMD_FLAGS_INTR BIT8(1) +#define PMU_CMD_FLAGS_EVENT BIT8(2) +#define PMU_CMD_FLAGS_WATERMARK BIT8(3) #define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1))