From f6c012b39dbd0b8ecb2f84ecdd41967ddc88c0b2 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Mon, 4 Feb 2019 15:51:17 -0500 Subject: [PATCH] gpu: nvgpu: lpwr: fix MISRA 10.3 violations MISRA Rule 10.3 prohibits implicit assignments of objects to different size or essential type. This fixes a number of these issues in common/pmu/lpwr. JIRA NVGPU-1008 Change-Id: Ia9cc0609f8c923cff38c9f85c2920aa60a522923 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2017605 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c | 24 ++++++++++++++-------- drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c | 6 ++++-- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h | 2 +- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c index 49d83cfa0..11d2c962b 100644 --- a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -235,7 +235,8 @@ static void nvgpu_pmu_handle_param_lpwr_msg(struct gk20a *g, int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate) { struct pmu_cmd cmd; - u32 seq, status = 0; + u32 seq; + int status = 0; u32 payload = NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED; struct clk_set_info *pstate_info; u32 ack_status = 0; @@ -255,11 +256,13 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate) } if (payload != g->perf_pmu->lpwr.mclk_change_cache) { + size_t tmp_size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_mclk_change); g->perf_pmu->lpwr.mclk_change_cache = payload; cmd.hdr.unit_id = PMU_UNIT_PG; - cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_pg_cmd_mclk_change); + nvgpu_assert(tmp_size <= U8_MAX); + cmd.hdr.size = (u8)(tmp_size); cmd.cmd.pg.mclk_change.cmd_type = PMU_PG_CMD_ID_PG_PARAM; cmd.cmd.pg.mclk_change.cmd_id = @@ -282,17 +285,20 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate) return status; } -u32 nvgpu_lpwr_post_init(struct gk20a *g) +int nvgpu_lpwr_post_init(struct gk20a *g) { struct pmu_cmd cmd; u32 seq; - u32 status = 0; + int status = 0; u32 ack_status = 0; + size_t tmp_size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_post_init_param); (void) memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; - cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_pg_cmd_post_init_param); + nvgpu_assert(tmp_size <= U8_MAX); + cmd.hdr.size = (u8)tmp_size; cmd.cmd.pg.post_init.cmd_type = PMU_PG_CMD_ID_PG_PARAM; @@ -364,7 +370,7 @@ bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num) int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock) { struct nvgpu_pmu *pmu = &g->pmu; - u32 status = 0; + int status = 0; bool is_mscg_supported = false; bool is_rppg_supported = false; u32 present_pstate = 0; diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c index b967f6a11..f5abb0d39 100644 --- a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "gp106/bios_gp106.h" @@ -54,11 +55,12 @@ static int rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd) u32 seq; int status = 0; u32 success = 0; + size_t tmp_size = PMU_CMD_HDR_SIZE + sizeof(struct nv_pmu_rppg_cmd); (void) memset(&cmd, 0, sizeof(struct pmu_cmd)); cmd.hdr.unit_id = PMU_UNIT_PG; - cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct nv_pmu_rppg_cmd); + nvgpu_assert(tmp_size <= U8_MAX); + cmd.hdr.size = (u8)tmp_size; cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG; cmd.cmd.pg.rppg_cmd.cmn.cmd_id = prppg_cmd->cmn.cmd_id; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 23b6d0fea..6e7c5a74b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1232,7 +1232,7 @@ struct gpu_ops { u32 feature_id); int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock); int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock); - u32 (*pmu_pg_param_post_init)(struct gk20a *g); + int (*pmu_pg_param_post_init)(struct gk20a *g); void (*dump_secure_fuses)(struct gk20a *g); int (*reset_engine)(struct gk20a *g, bool do_reset); bool (*is_engine_in_reset)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h index 332e1b6b9..12f514293 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h @@ -96,7 +96,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock); int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock); bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num); bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); -u32 nvgpu_lpwr_post_init(struct gk20a *g); +int nvgpu_lpwr_post_init(struct gk20a *g); int init_rppg(struct gk20a *g);