diff --git a/drivers/gpu/nvgpu/common/gr/fecs_trace.c b/drivers/gpu/nvgpu/common/gr/fecs_trace.c
index e97360cae..f1b049723 100644
--- a/drivers/gpu/nvgpu/common/gr/fecs_trace.c
+++ b/drivers/gpu/nvgpu/common/gr/fecs_trace.c
@@ -646,7 +646,7 @@ int nvgpu_gr_fecs_trace_bind_channel(struct gk20a *g,
 		GK20A_FECS_TRACE_NUM_RECORDS);
 
 	if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_VA) && subctx != NULL) {
-		mem = nvgpu_gr_subctx_get_ctx_header(g, subctx);
+		mem = nvgpu_gr_subctx_get_ctx_header(subctx);
 	}
 
 	g->ops.gr.ctxsw_prog.set_ts_buffer_ptr(g, mem, addr, aperture_mask);
diff --git a/drivers/gpu/nvgpu/common/gr/gr_config.c b/drivers/gpu/nvgpu/common/gr/gr_config.c
index 6e235d7a8..27ff3071b 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_config.c
+++ b/drivers/gpu/nvgpu/common/gr/gr_config.c
@@ -54,8 +54,7 @@ static void gr_config_init_pes_tpc(struct gk20a *g,
 	}
 }
 
-static void gr_config_init_gpc_skip_mask(struct gk20a *g,
-					struct nvgpu_gr_config *config,
+static void gr_config_init_gpc_skip_mask(struct nvgpu_gr_config *config,
 					u32 gpc_index)
 {
 	u32 pes_heavy_index;
@@ -327,7 +326,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
 		config->ppc_count = nvgpu_safe_add_u32(config->ppc_count,
 					config->gpc_ppc_count[gpc_index]);
 
-		gr_config_init_gpc_skip_mask(g, config, gpc_index);
+		gr_config_init_gpc_skip_mask(config, gpc_index);
 	}
 
 	gr_config_log_info(g, config);
diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr.c b/drivers/gpu/nvgpu/common/gr/gr_intr.c
index ed3ea01e2..04e4ec6fc 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_intr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr_intr.c
@@ -720,7 +720,7 @@ void nvgpu_gr_intr_handle_semaphore_pending(struct gk20a *g,
 }
 
 static u32 gr_intr_handle_exception_interrupts(struct gk20a *g,
-		u32 gr_intr, u32 *clear_intr,
+		u32 *clear_intr,
 		struct nvgpu_tsg *tsg, u32 *global_esr,
 		struct nvgpu_gr_intr_info *intr_info,
 		struct nvgpu_gr_isr_data *isr_data)
@@ -949,8 +949,8 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g)
 	need_reset |= gr_intr_handle_error_interrupts(g, gr_intr,
 				&clear_intr, &intr_info, &isr_data);
 
-	need_reset |= gr_intr_handle_exception_interrupts(g, gr_intr,
-			&clear_intr, tsg, &global_esr, &intr_info, &isr_data);
+	need_reset |= gr_intr_handle_exception_interrupts(g, &clear_intr,
+				tsg, &global_esr, &intr_info, &isr_data);
 
 	if (need_reset != 0U) {
 		nvgpu_rc_gr_fault(g, tsg, isr_data.ch);
diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
index 23147ad7e..394b85b96 100644
--- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c
+++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
@@ -56,7 +56,7 @@ void nvgpu_gr_obj_ctx_commit_inst(struct gk20a *g, struct nvgpu_mem *inst_block,
 	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) {
 		nvgpu_gr_subctx_load_ctx_header(g, subctx, gr_ctx, gpu_va);
 
-		ctxheader = nvgpu_gr_subctx_get_ctx_header(g, subctx);
+		ctxheader = nvgpu_gr_subctx_get_ctx_header(subctx);
 		nvgpu_gr_obj_ctx_commit_inst_gpu_va(g, inst_block,
 			ctxheader->gpu_va);
 	} else {
diff --git a/drivers/gpu/nvgpu/common/gr/subctx.c b/drivers/gpu/nvgpu/common/gr/subctx.c
index ba974a3c3..a16c867bc 100644
--- a/drivers/gpu/nvgpu/common/gr/subctx.c
+++ b/drivers/gpu/nvgpu/common/gr/subctx.c
@@ -123,8 +123,7 @@ void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g,
 		 nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx)->gpu_va);
 }
 
-struct nvgpu_mem *nvgpu_gr_subctx_get_ctx_header(struct gk20a *g,
-		struct nvgpu_gr_subctx *subctx)
+struct nvgpu_mem *nvgpu_gr_subctx_get_ctx_header(struct nvgpu_gr_subctx *subctx)
 {
 	return &subctx->ctx_header;
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h
index 48ceb32e8..045315dfa 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h
@@ -43,8 +43,7 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g,
 void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g,
 	struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx);
 
-struct nvgpu_mem *nvgpu_gr_subctx_get_ctx_header(struct gk20a *g,
-	struct nvgpu_gr_subctx *subctx);
+struct nvgpu_mem *nvgpu_gr_subctx_get_ctx_header(struct nvgpu_gr_subctx *subctx);
 
 #ifdef CONFIG_NVGPU_GRAPHICS
 void nvgpu_gr_subctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx,