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gpu: nvgpu: fix fll regime check

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For target clocks >= FFR cutoff clock use FR, else use FFR.

JIRA DNVGPU-180

Change-Id: Iefed871d2acf1552230b066c32e1b3f69d96079e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1249041
(cherry picked from commit edcb12d8784c62aa857dcab2e27d4e45033fbf11)
Reviewed-on: http://git-master/r/1270883
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vijayakumar
2016-11-07 18:12:19 +05:30
committed by Deepak Nibade
parent 8edfc9ee67
commit f7290e6a83
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/nvgpu/clk/clk.c
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@@ -288,9 +288,9 @@ static u32 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz)
if (pflldev->clk_domain == domain) {
if (pflldev->regime_desc.fixed_freq_regime_limit_mhz >=
clkmhz)
return CTRL_CLK_FLL_REGIME_ID_FR;
else
return CTRL_CLK_FLL_REGIME_ID_FFR;
else
return CTRL_CLK_FLL_REGIME_ID_FR;
}
}
return CTRL_CLK_FLL_REGIME_ID_INVALID;