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gpu: nvgpu: unit: use allocated IO reg spaces
Statically initialized nvgpu_posix_io_reg_space structures are used in test_fifo_setup_gv11b_reg_space to initialize register spaces. If fifo, TSG and channel unit tests run concurrently, the same register space structure can be registered multiple times for different GPU contexts. This results in list corruption or use of freed memory. Use allocated register spaces instead. Jira NVGPU-3943 Change-Id: I74c080f336e32149d2a378e2b15d37a2bd60ff71 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2204062 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
This commit is contained in:
Thomas Fleury
committed by
Alex Waterman
Alex Waterman
parent
10094b7091
commit
f779eb8e9a
@@ -33,6 +33,8 @@
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#include "hal/fuse/fuse_gm20b.h"
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#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
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#include "nvgpu-fifo-gv11b.h"
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u32 gv11b_fuse_regs[] = {
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@@ -294,12 +296,6 @@ u32 gv11b_fuse_regs[] = {
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/* 0x00021ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
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};
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struct nvgpu_posix_io_reg_space gv11b_fuse_reg_space = {
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.base = 0x00021000,
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.size = sizeof(gv11b_fuse_regs),
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.data = gv11b_fuse_regs,
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};
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u32 gv11b_master_regs[] = {
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/* 0x00000000 */ 0x15b000a1, 0x00000000, 0x00000000, 0xbadf5040,
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/* 0x00000010 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
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@@ -559,13 +555,6 @@ u32 gv11b_master_regs[] = {
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/* 0x00000ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
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};
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struct nvgpu_posix_io_reg_space gv11b_master_reg_space = {
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.base = 0x00000000,
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.size = sizeof(gv11b_master_regs),
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.data = gv11b_master_regs,
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};
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u32 gv11b_top_regs[] = {
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/* 0x00022400 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
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/* 0x00022410 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0x00000081,
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@@ -633,12 +622,6 @@ u32 gv11b_top_regs[] = {
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/* 0x000227f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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};
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struct nvgpu_posix_io_reg_space gv11b_top_reg_space = {
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.base = 0x22400,
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.size = sizeof(gv11b_top_regs),
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.data = gv11b_top_regs,
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};
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u32 gv11b_fifo_regs[] = {
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/* 0x00002000 */ 0x00000000, 0x00200003, 0x00000200, 0x0000c36f,
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/* 0x00002010 */ 0x0000000f, 0xbadf5040, 0xbadf5040, 0xbadf5040,
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@@ -1154,12 +1137,6 @@ u32 gv11b_fifo_regs[] = {
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/* 0x00003ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
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};
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struct nvgpu_posix_io_reg_space gv11b_fifo_reg_space = {
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.base = 0x2000,
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.size = sizeof(gv11b_fifo_regs),
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.data = gv11b_fifo_regs,
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};
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u32 gv11b_pbdma_regs[] = {
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/* 0x00040000 */ 0x00000003, 0x00000000, 0x1cd05e03, 0x00000008,
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/* 0x00040010 */ 0x0000c36f, 0x00000003, 0x00408050, 0x0000001f,
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@@ -9355,12 +9332,6 @@ u32 gv11b_pbdma_regs[] = {
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/* 0x0005fff0 */ 0xbad00100, 0xbad00100, 0xbad00100, 0xbad00100,
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};
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struct nvgpu_posix_io_reg_space gv11b_pbdma_reg_space = {
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.base = 0x00040000,
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.size = sizeof(gv11b_pbdma_regs),
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.data = gv11b_pbdma_regs,
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};
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u32 gv11b_ccsr_regs[] = {
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/* 0x00800000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 0x00800010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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@@ -13460,17 +13431,6 @@ u32 gv11b_ccsr_regs[] = {
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/* 0x0080fff0 */ 0xbad00100, 0xbad00100, 0xbad00100, 0xbad00100,
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};
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struct nvgpu_posix_io_reg_space gv11b_ccsr_reg_space = {
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.base = 0x00800000,
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.size = sizeof(gv11b_ccsr_regs),
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.data = gv11b_ccsr_regs,
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};
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struct nvgpu_posix_io_reg_space gv11b_usermode_reg_space = {
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.base = 0x00810000,
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.size = 0x10000,
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.data = NULL,
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};
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/*
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* Mock I/O
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*/
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@@ -13516,97 +13476,140 @@ static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
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.tegra_fuse_readl = tegra_fuse_readl_access_reg_fn,
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};
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#define fifo_array_reg_space(x) sizeof(x)/sizeof(struct nvgpu_posix_io_reg_space)
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struct nvgpu_posix_io_reg_space fifo_gv11b_initialized_reg_space[] = {
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[0] = { /* FUSE */
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.base = 0x00021000,
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.size = sizeof(gv11b_fuse_regs),
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.data = gv11b_fuse_regs,
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},
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[1] = { /* MASTER */
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.base = 0x00000000,
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.size = sizeof(gv11b_master_regs),
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.data = gv11b_master_regs,
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},
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[2] = { /* TOP */
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.base = 0x22400,
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.size = sizeof(gv11b_top_regs),
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.data = gv11b_top_regs,
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},
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[3] = { /* PBDMA */
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.base = 0x00040000,
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.size = sizeof(gv11b_pbdma_regs),
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.data = gv11b_pbdma_regs,
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},
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[4] = { /* CCSR */
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.base = 0x00800000,
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.size = sizeof(gv11b_ccsr_regs),
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.data = gv11b_ccsr_regs,
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},
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[5] = { /* FIFO */
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.base = 0x2000,
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.size = sizeof(gv11b_fifo_regs),
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.data = gv11b_fifo_regs,
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}
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};
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struct nvgpu_posix_io_reg_space gv11b_usermode_reg_space = {
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.base = 0x00810000,
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.size = 0x10000,
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.data = NULL,
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};
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static void fifo_io_delete_initialized_reg_space(struct unit_module *m, struct gk20a *g)
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{
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u32 i = 0;
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u32 arr_size = fifo_array_reg_space(fifo_gv11b_initialized_reg_space);
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for (i = 0; i < arr_size; i++) {
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u32 base = fifo_gv11b_initialized_reg_space[i].base;
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nvgpu_posix_io_delete_reg_space(g, base);
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}
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}
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static int fifo_io_add_initialized_reg_space(struct unit_module *m, struct gk20a *g)
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{
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int ret = 0;
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u32 arr_size = fifo_array_reg_space(fifo_gv11b_initialized_reg_space);
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u32 i = 0, j = 0;
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u32 base, size;
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struct nvgpu_posix_io_reg_space *reg_space;
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for (i = 0; i < arr_size; i++) {
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base = fifo_gv11b_initialized_reg_space[i].base;
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size = fifo_gv11b_initialized_reg_space[i].size;
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if (nvgpu_posix_io_add_reg_space(g, base, size) != 0) {
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unit_err(m, "failed to add reg space for %08x\n", base);
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ret = -ENOMEM;
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goto clean_init_reg_space;
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}
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reg_space = nvgpu_posix_io_get_reg_space(g, base);
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if (reg_space == NULL) {
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unit_err(m, "failed to get reg space for %08x\n", base);
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ret = -EINVAL;
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goto clean_init_reg_space;
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}
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memcpy(reg_space->data, fifo_gv11b_initialized_reg_space[i].data, size);
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}
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return ret;
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clean_init_reg_space:
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for (j = 0; j < i; j++) {
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base = fifo_gv11b_initialized_reg_space[j].base;
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nvgpu_posix_io_delete_reg_space(g, base);
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}
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return ret;
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}
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int test_fifo_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
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{
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u32 i;
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struct nvgpu_posix_io_reg_space *reg_space;
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/* Create register space */
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nvgpu_posix_io_init_reg_space(g);
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if (nvgpu_posix_io_register_reg_space(g,
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&gv11b_master_reg_space) != 0) {
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unit_err(m, "%s: failed to create master register space\n",
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__func__);
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if (fifo_io_add_initialized_reg_space(m, g) != 0) {
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unit_err(m, "failed to get initialized reg space\n");
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return UNIT_FAIL;
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}
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if (nvgpu_posix_io_register_reg_space(g, &gv11b_top_reg_space) != 0) {
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unit_err(m, "%s: failed to create top register space\n",
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__func__);
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goto clean_up_master;
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/* USERMODE reg space */
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if (nvgpu_posix_io_add_reg_space(g, usermode_cfg0_r(), 0x10000) != 0) {
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unit_err(m, "Add USERMODE reg space failed!\n");
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goto clean_up_reg_space;
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}
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if (nvgpu_posix_io_register_reg_space(g, &gv11b_fifo_reg_space) != 0) {
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unit_err(m, "%s: failed to create fifo register space\n",
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__func__);
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goto clean_up_top;
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reg_space = nvgpu_posix_io_get_reg_space(g, usermode_cfg0_r());
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if (reg_space == NULL) {
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unit_err(m, "failed to get reg space for %08x\n",
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usermode_cfg0_r());
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goto clean_up_reg_space;
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}
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if (nvgpu_posix_io_register_reg_space(g, &gv11b_pbdma_reg_space) != 0) {
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unit_err(m, "%s: failed to create pbdma register space\n",
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__func__);
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goto clean_up_fifo;
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}
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if (nvgpu_posix_io_register_reg_space(g, &gv11b_ccsr_reg_space) != 0) {
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unit_err(m, "%s: failed to create ccsr register space\n",
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__func__);
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goto clean_up_pbdma;
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}
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if (nvgpu_posix_io_register_reg_space(g, &gv11b_fuse_reg_space) != 0) {
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unit_err(m, "%s: failed to create fuse register space\n",
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__func__);
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goto clean_up_ccsr;
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}
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gv11b_usermode_reg_space.data = nvgpu_vzalloc(g,
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gv11b_usermode_reg_space.size);
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if (gv11b_usermode_reg_space.data == NULL) {
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unit_err(m, "%s: failed to allocate usermode register space\n",
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__func__);
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goto clean_up_fuse;
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}
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for (i = 0U; i < gv11b_usermode_reg_space.size / 4U; i++) {
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gv11b_usermode_reg_space.data[i] = 0xbadf1100;
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}
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if (nvgpu_posix_io_register_reg_space(g,
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&gv11b_usermode_reg_space) != 0) {
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unit_err(m, "%s: failed to create usermode register space\n",
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__func__);
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goto clean_up_usermode;
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for (i = 0U; i < reg_space->size / 4U; i++) {
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reg_space->data[i] = 0xbadf1100;
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}
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(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
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return 0;
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clean_up_usermode:
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nvgpu_vfree(g, gv11b_usermode_reg_space.data);
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clean_up_fuse:
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_fuse_reg_space);
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clean_up_ccsr:
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_ccsr_reg_space);
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clean_up_pbdma:
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_pbdma_reg_space);
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clean_up_fifo:
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_fifo_reg_space);
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clean_up_top:
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space);
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clean_up_master:
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space);
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clean_up_reg_space:
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nvgpu_posix_io_delete_reg_space(g, usermode_cfg0_r());
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fifo_io_delete_initialized_reg_space(m, g);
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return -ENOMEM;
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}
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void test_fifo_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
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{
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space);
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space);
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_fifo_reg_space);
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_pbdma_reg_space);
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_ccsr_reg_space);
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nvgpu_vfree(g, gv11b_usermode_reg_space.data);
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nvgpu_posix_io_unregister_reg_space(g, &gv11b_usermode_reg_space);
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nvgpu_posix_io_delete_reg_space(g, usermode_cfg0_r());
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fifo_io_delete_initialized_reg_space(m, g);
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}
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