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gpu: nvgpu: move .runlist.hw_submit to use runlist_id

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Use detailed function parameters runlist_id, iova/aperture and count, so
the HAL could be reused on server side.

Jira GVSCI-15773

Change-Id: I28f68682b9eea4e798af5c850c87840bd9b79970
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Richard Zhao
2023-02-21 19:10:28 -08:00
committed by mobile promotions
parent a587d94f5a
commit f791adf880
13 changed files with 79 additions and 52 deletions
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11
drivers/gpu/nvgpu/common/fifo/runlist.c
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@@ -756,7 +756,7 @@ static void nvgpu_runlist_domain_actual_submit(struct gk20a *g, struct nvgpu_run
* and domain mem swaps. * and domain mem swaps.
*/ */
nvgpu_spinlock_acquire(&rl->domain->lock); nvgpu_spinlock_acquire(&rl->domain->lock);
g->ops.runlist.hw_submit(g, rl); nvgpu_runlist_hw_submit(g, rl);
nvgpu_spinlock_release(&rl->domain->lock); nvgpu_spinlock_release(&rl->domain->lock);
} }
@@ -1480,3 +1480,12 @@ struct nvgpu_runlist_domain *nvgpu_runlist_get_shadow_domain(struct gk20a *g)
{ {
return g->fifo.active_runlists[0].shadow_rl_domain; return g->fifo.active_runlists[0].shadow_rl_domain;
} }
void nvgpu_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist)
{
u64 runlist_iova = nvgpu_mem_get_addr(g, &runlist->domain->mem_hw->mem);
enum nvgpu_aperture aperture = runlist->domain->mem_hw->mem.aperture;
u32 count = runlist->domain->mem_hw->count;
g->ops.runlist.hw_submit(g, runlist->id, runlist_iova, aperture, count);
}

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100.h
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@@ -1,7 +1,7 @@
/* /*
* GA100 runlist * GA100 runlist
* *
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -30,5 +30,6 @@
struct gk20a; struct gk20a;
u32 ga100_runlist_count_max(struct gk20a *g); u32 ga100_runlist_count_max(struct gk20a *g);
void ga100_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist); void ga100_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count);
#endif /* NVGPU_RUNLIST_FIFO_GA100_H */ #endif /* NVGPU_RUNLIST_FIFO_GA100_H */

15
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga100_fusa.c
View File

@@ -1,7 +1,7 @@
/* /*
* GA100 Runlist * GA100 Runlist
* *
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -38,20 +38,21 @@ u32 ga100_runlist_count_max(struct gk20a *g)
return nvgpu_get_litter_value(g, GPU_LIT_MAX_RUNLISTS_SUPPORTED); return nvgpu_get_litter_value(g, GPU_LIT_MAX_RUNLISTS_SUPPORTED);
} }
void ga100_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist) void ga100_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count)
{ {
u64 runlist_iova; struct nvgpu_runlist *runlist = g->fifo.runlists[runlist_id];
u32 runlist_iova_lo, runlist_iova_hi; u32 runlist_iova_lo, runlist_iova_hi;
runlist_iova = nvgpu_mem_get_addr(g, &runlist->domain->mem_hw->mem);
runlist_iova_lo = u64_lo32(runlist_iova) >> runlist_iova_lo = u64_lo32(runlist_iova) >>
runlist_submit_base_lo_ptr_align_shift_v(); runlist_submit_base_lo_ptr_align_shift_v();
runlist_iova_hi = u64_hi32(runlist_iova); runlist_iova_hi = u64_hi32(runlist_iova);
if (runlist->domain->mem_hw->count != 0U) { if (count != 0U) {
nvgpu_runlist_writel(g, runlist, runlist_submit_base_lo_r(), nvgpu_runlist_writel(g, runlist, runlist_submit_base_lo_r(),
runlist_submit_base_lo_ptr_lo_f(runlist_iova_lo) | runlist_submit_base_lo_ptr_lo_f(runlist_iova_lo) |
nvgpu_aperture_mask(g, &runlist->domain->mem_hw->mem, nvgpu_aperture_mask_raw(g, aperture,
runlist_submit_base_lo_target_sys_mem_noncoherent_f(), runlist_submit_base_lo_target_sys_mem_noncoherent_f(),
runlist_submit_base_lo_target_sys_mem_coherent_f(), runlist_submit_base_lo_target_sys_mem_coherent_f(),
runlist_submit_base_lo_target_vid_mem_f())); runlist_submit_base_lo_target_vid_mem_f()));
@@ -63,5 +64,5 @@ void ga100_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist)
/* TODO offset in runlist support */ /* TODO offset in runlist support */
nvgpu_runlist_writel(g, runlist, runlist_submit_r(), nvgpu_runlist_writel(g, runlist, runlist_submit_r(),
runlist_submit_offset_f(0U) | runlist_submit_offset_f(0U) |
runlist_submit_length_f(runlist->domain->mem_hw->count)); runlist_submit_length_f(count));
} }

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b.h
View File

@@ -1,7 +1,7 @@
/* /*
* GA10B runlist * GA10B runlist
* *
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -32,7 +32,8 @@ struct nvgpu_runlist;
u32 ga10b_runlist_count_max(struct gk20a *g); u32 ga10b_runlist_count_max(struct gk20a *g);
u32 ga10b_runlist_length_max(struct gk20a *g); u32 ga10b_runlist_length_max(struct gk20a *g);
void ga10b_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist); void ga10b_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count);
int ga10b_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist); int ga10b_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist);
void ga10b_runlist_write_state(struct gk20a *g, u32 runlists_mask, void ga10b_runlist_write_state(struct gk20a *g, u32 runlists_mask,
u32 runlist_state); u32 runlist_state);

18
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_ga10b_fusa.c
View File

@@ -1,7 +1,7 @@
/* /*
* GA10B Runlist * GA10B Runlist
* *
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -50,20 +50,20 @@ u32 ga10b_runlist_length_max(struct gk20a *g)
return runlist_submit_length_max_v(); return runlist_submit_length_max_v();
} }
void ga10b_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist) void ga10b_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count)
{ {
u64 runlist_iova; struct nvgpu_runlist *runlist = g->fifo.runlists[runlist_id];
u32 runlist_iova_lo, runlist_iova_hi; u32 runlist_iova_lo, runlist_iova_hi;
runlist_iova = nvgpu_mem_get_addr(g, &runlist->domain->mem_hw->mem);
runlist_iova_lo = u64_lo32(runlist_iova) >> runlist_iova_lo = u64_lo32(runlist_iova) >>
runlist_submit_base_lo_ptr_align_shift_v(); runlist_submit_base_lo_ptr_align_shift_v();
runlist_iova_hi = u64_hi32(runlist_iova); runlist_iova_hi = u64_hi32(runlist_iova);
if (runlist->domain->mem_hw->count != 0U) { if (count != 0U) {
nvgpu_runlist_writel(g, runlist, runlist_submit_base_lo_r(), nvgpu_runlist_writel(g, runlist, runlist_submit_base_lo_r(),
runlist_submit_base_lo_ptr_lo_f(runlist_iova_lo) | runlist_submit_base_lo_ptr_lo_f(runlist_iova_lo) |
nvgpu_aperture_mask(g, &runlist->domain->mem_hw->mem, nvgpu_aperture_mask_raw(g, aperture,
runlist_submit_base_lo_target_sys_mem_noncoherent_f(), runlist_submit_base_lo_target_sys_mem_noncoherent_f(),
runlist_submit_base_lo_target_sys_mem_coherent_f(), runlist_submit_base_lo_target_sys_mem_coherent_f(),
runlist_submit_base_lo_target_vid_mem_f())); runlist_submit_base_lo_target_vid_mem_f()));
@@ -72,13 +72,13 @@ void ga10b_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist)
runlist_submit_base_hi_ptr_hi_f(runlist_iova_hi)); runlist_submit_base_hi_ptr_hi_f(runlist_iova_hi));
} }
rl_dbg(g, "Submitting domain[%llu], mem=0x%16llx", runlist->domain->domain_id, rl_dbg(g, "Submitting runlist[%d], mem=0x%16llx", runlist_id,
(u64)nvgpu_mem_get_addr(g, &runlist->domain->mem_hw->mem)); (u64)runlist_iova);
/* TODO offset in runlist support */ /* TODO offset in runlist support */
nvgpu_runlist_writel(g, runlist, runlist_submit_r(), nvgpu_runlist_writel(g, runlist, runlist_submit_r(),
runlist_submit_offset_f(0U) | runlist_submit_offset_f(0U) |
runlist_submit_length_f(runlist->domain->mem_hw->count)); runlist_submit_length_f(count));
} }
int ga10b_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist) int ga10b_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist)

6
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -29,6 +29,7 @@ struct nvgpu_channel;
struct nvgpu_tsg; struct nvgpu_tsg;
struct gk20a; struct gk20a;
struct nvgpu_runlist; struct nvgpu_runlist;
enum nvgpu_aperture;
#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING #ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
int gk20a_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next); int gk20a_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next);
@@ -40,7 +41,8 @@ u32 gk20a_runlist_count_max(struct gk20a *g);
#endif #endif
u32 gk20a_runlist_length_max(struct gk20a *g); u32 gk20a_runlist_length_max(struct gk20a *g);
void gk20a_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist); void gk20a_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count);
int gk20a_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist); int gk20a_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist);
void gk20a_runlist_write_state(struct gk20a *g, u32 runlists_mask, void gk20a_runlist_write_state(struct gk20a *g, u32 runlists_mask,
u32 runlist_state); u32 runlist_state);

15
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a_fusa.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -39,24 +39,23 @@ u32 gk20a_runlist_length_max(struct gk20a *g)
return fifo_eng_runlist_length_max_v(); return fifo_eng_runlist_length_max_v();
} }
void gk20a_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist) void gk20a_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count)
{ {
u64 runlist_iova = nvgpu_mem_get_addr(g, &runlist->domain->mem_hw->mem);
nvgpu_spinlock_acquire(&g->fifo.runlist_submit_lock); nvgpu_spinlock_acquire(&g->fifo.runlist_submit_lock);
if (runlist->domain->mem_hw->count != 0U) { if (count != 0U) {
nvgpu_writel(g, fifo_runlist_base_r(), nvgpu_writel(g, fifo_runlist_base_r(),
fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12U)) | fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12U)) |
nvgpu_aperture_mask(g, &runlist->domain->mem_hw->mem, nvgpu_aperture_mask_raw(g, aperture,
fifo_runlist_base_target_sys_mem_ncoh_f(), fifo_runlist_base_target_sys_mem_ncoh_f(),
fifo_runlist_base_target_sys_mem_coh_f(), fifo_runlist_base_target_sys_mem_coh_f(),
fifo_runlist_base_target_vid_mem_f())); fifo_runlist_base_target_vid_mem_f()));
} }
nvgpu_writel(g, fifo_runlist_r(), nvgpu_writel(g, fifo_runlist_r(),
fifo_runlist_engine_f(runlist->id) | fifo_runlist_engine_f(runlist_id) |
fifo_eng_runlist_length_f(runlist->domain->mem_hw->count)); fifo_eng_runlist_length_f(count));
nvgpu_spinlock_release(&g->fifo.runlist_submit_lock); nvgpu_spinlock_release(&g->fifo.runlist_submit_lock);
} }

20
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -34,31 +34,29 @@ u32 tu104_runlist_count_max(struct gk20a *g)
return fifo_runlist_base_lo__size_1_v(); return fifo_runlist_base_lo__size_1_v();
} }
void tu104_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist) void tu104_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count)
{ {
u64 runlist_iova;
u32 runlist_iova_lo, runlist_iova_hi; u32 runlist_iova_lo, runlist_iova_hi;
runlist_iova = nvgpu_mem_get_addr(g, &runlist->domain->mem_hw->mem);
runlist_iova_lo = u64_lo32(runlist_iova) >> runlist_iova_lo = u64_lo32(runlist_iova) >>
fifo_runlist_base_lo_ptr_align_shift_v(); fifo_runlist_base_lo_ptr_align_shift_v();
runlist_iova_hi = u64_hi32(runlist_iova); runlist_iova_hi = u64_hi32(runlist_iova);
if (runlist->domain->mem_hw->count != 0U) { if (count != 0U) {
nvgpu_writel(g, fifo_runlist_base_lo_r(runlist->id), nvgpu_writel(g, fifo_runlist_base_lo_r(runlist_id),
fifo_runlist_base_lo_ptr_lo_f(runlist_iova_lo) | fifo_runlist_base_lo_ptr_lo_f(runlist_iova_lo) |
nvgpu_aperture_mask(g, &runlist->domain->mem_hw->mem, nvgpu_aperture_mask_raw(g, aperture,
fifo_runlist_base_lo_target_sys_mem_ncoh_f(), fifo_runlist_base_lo_target_sys_mem_ncoh_f(),
fifo_runlist_base_lo_target_sys_mem_coh_f(), fifo_runlist_base_lo_target_sys_mem_coh_f(),
fifo_runlist_base_lo_target_vid_mem_f())); fifo_runlist_base_lo_target_vid_mem_f()));
nvgpu_writel(g, fifo_runlist_base_hi_r(runlist->id), nvgpu_writel(g, fifo_runlist_base_hi_r(runlist_id),
fifo_runlist_base_hi_ptr_hi_f(runlist_iova_hi)); fifo_runlist_base_hi_ptr_hi_f(runlist_iova_hi));
} }
nvgpu_writel(g, fifo_runlist_submit_r(runlist->id), nvgpu_writel(g, fifo_runlist_submit_r(runlist_id),
fifo_runlist_submit_length_f(runlist->domain->mem_hw->count)); fifo_runlist_submit_length_f(count));
} }
int tu104_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist) int tu104_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist)

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -29,7 +29,8 @@ struct gk20a;
struct nvgpu_runlist; struct nvgpu_runlist;
u32 tu104_runlist_count_max(struct gk20a *g); u32 tu104_runlist_count_max(struct gk20a *g);
void tu104_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist); void tu104_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count);
int tu104_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist); int tu104_runlist_check_pending(struct gk20a *g, struct nvgpu_runlist *runlist);
#endif /* NVGPU_RUNLIST_FIFO_TU104_H */ #endif /* NVGPU_RUNLIST_FIFO_TU104_H */

5
drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -92,7 +92,8 @@ struct gops_runlist {
void (*get_tsg_entry)(struct nvgpu_tsg *tsg, void (*get_tsg_entry)(struct nvgpu_tsg *tsg,
u32 *runlist, u32 timeslice); u32 *runlist, u32 timeslice);
void (*get_ch_entry)(struct nvgpu_channel *ch, u32 *runlist); void (*get_ch_entry)(struct nvgpu_channel *ch, u32 *runlist);
void (*hw_submit)(struct gk20a *g, struct nvgpu_runlist *runlist); void (*hw_submit)(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count);
int (*check_pending)(struct gk20a *g, struct nvgpu_runlist *runlist); int (*check_pending)(struct gk20a *g, struct nvgpu_runlist *runlist);
void (*write_state)(struct gk20a *g, u32 runlists_mask, void (*write_state)(struct gk20a *g, u32 runlists_mask,
u32 runlist_state); u32 runlist_state);

8
drivers/gpu/nvgpu/include/nvgpu/runlist.h
View File

@@ -338,6 +338,14 @@ int nvgpu_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next,
int nvgpu_runlist_update(struct gk20a *g, struct nvgpu_runlist *rl, int nvgpu_runlist_update(struct gk20a *g, struct nvgpu_runlist *rl,
struct nvgpu_channel *ch, bool add, bool wait_for_finish); struct nvgpu_channel *ch, bool add, bool wait_for_finish);
/**
* @brief Submit runlist to hardware.
*
* @param g [in] The GPU driver struct owning this runlist.
* @param runlist [in] Runlist object to be submited.
*/
void nvgpu_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist);
/** /**
* @brief Reload runlist * @brief Reload runlist
* *

10
userspace/units/fifo/runlist/gk20a/nvgpu-runlist-gk20a.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -78,7 +78,7 @@ int test_gk20a_runlist_hw_submit(struct unit_module *m,
struct nvgpu_fifo *f = &g->fifo; struct nvgpu_fifo *f = &g->fifo;
int ret = UNIT_FAIL; int ret = UNIT_FAIL;
u32 runlist_id = nvgpu_engine_get_gr_runlist_id(g); u32 runlist_id = nvgpu_engine_get_gr_runlist_id(g);
struct nvgpu_runlist *runlist = g->fifo.runlists[runlist_id]; struct nvgpu_runlist *runlist = f->runlists[runlist_id];
u32 count; u32 count;
for (count = 0; count < 2; count++) { for (count = 0; count < 2; count++) {
@@ -88,7 +88,11 @@ int test_gk20a_runlist_hw_submit(struct unit_module *m,
runlist->domain->mem_hw->count = count; runlist->domain->mem_hw->count = count;
gk20a_runlist_hw_submit(g, f->runlists[runlist_id]); gk20a_runlist_hw_submit(g,
runlist_id,
nvgpu_mem_get_addr(g, &runlist->domain->mem_hw->mem),
runlist->domain->mem_hw->mem.aperture,
runlist->domain->mem_hw->count);
if (count == 0) { if (count == 0) {
unit_assert(nvgpu_readl(g, fifo_runlist_base_r()) == 0, unit_assert(nvgpu_readl(g, fifo_runlist_base_r()) == 0,
goto done); goto done);

8
userspace/units/nvs/nvgpu-nvs.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -119,9 +119,11 @@ static int stub_runlist_update(struct gk20a *g, struct nvgpu_runlist *rl,
return 0; return 0;
} }
static void stub_runlist_hw_submit(struct gk20a *g, struct nvgpu_runlist *runlist) static void stub_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u64 runlist_iova, enum nvgpu_aperture aperture, u32 count)
{ {
struct nvgpu_runlist_domain *domain = runlist->domain; struct nvgpu_runlist_domain *domain =
g->fifo.runlists[runlist_id]->domain;
nvs_context.updated_domain = domain; nvs_context.updated_domain = domain;
} }