From f7a169e7f390913eeda6813abe3218f034f4cd15 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 4 Apr 2019 15:21:55 +0530 Subject: [PATCH] gpu: nvgpu: move PG code from pmu_gk20a/gp106.c/h to PG unit As part of PMU HAL separation, need to move non-HAL code to respective UNIT & found still some more PG code left in these pmu_gk20a/gp106.c/h files which needs to be moved PG UNIT. JIRA NVGPU-2002 Change-Id: I583c3da35aff788f1bc0451af0b0dbdab0a62c00 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/2089870 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.c | 110 ++++++++++++++++++ drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.h | 39 +++++++ drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c | 34 ++++++ drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.h | 2 + drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c | 76 ------------ drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h | 7 -- drivers/gpu/nvgpu/common/pmu/pmu_gp106.c | 37 ------ drivers/gpu/nvgpu/common/pmu/pmu_gp106.h | 2 - drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 9 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 7 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 8 -- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 7 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 8 -- 15 files changed, 200 insertions(+), 148 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.c create mode 100644 drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 5d4798a93..567c7dfdf 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -88,6 +88,7 @@ nvgpu-y += \ common/pmu/pmu_gp10b.o \ common/pmu/pmu_gp106.o \ common/pmu/pmu_gv11b.o \ + common/pmu/pg/pg_sw_gm20b.o \ common/pmu/pg/pg_sw_gp10b.o \ common/pmu/pg/pg_sw_gp106.o \ common/pmu/pg/pg_sw_gv11b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 36d6adca2..37ee5159e 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -133,6 +133,7 @@ srcs += common/sim.c \ common/pmu/pmu_gp10b.c \ common/pmu/pmu_gp106.c \ common/pmu/pmu_gv11b.c \ + common/pmu/pg/pg_sw_gm20b.c \ common/pmu/pg/pg_sw_gp10b.c \ common/pmu/pg/pg_sw_gp106.c \ common/pmu/pg/pg_sw_gv11b.c \ diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.c new file mode 100644 index 000000000..2ee16f60c --- /dev/null +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "pg_sw_gm20b.h" + +u32 gm20b_pmu_pg_engines_list(struct gk20a *g) +{ + return BIT32(PMU_PG_ELPG_ENGINE_ID_GRAPHICS); +} + +u32 gm20b_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) +{ + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + return NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; + } + + return 0; +} + +static void pmu_handle_zbc_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 status) +{ + struct nvgpu_pmu *pmu = param; + nvgpu_pmu_dbg(g, "reply ZBC_TABLE_UPDATE"); + pmu->pmu_pg.zbc_save_done = true; +} + +void gm20b_pmu_save_zbc(struct gk20a *g, u32 entries) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct pmu_cmd cmd; + size_t tmp_size; + int err = 0; + + if (!pmu->pmu_ready || (entries == 0U) || !pmu->pmu_pg.zbc_ready) { + return; + } + + (void) memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + tmp_size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_zbc_cmd); + nvgpu_assert(tmp_size <= (size_t)U8_MAX); + cmd.hdr.size = (u8)tmp_size; + cmd.cmd.zbc.cmd_type = g->pmu_ver_cmd_id_zbc_table_update; + cmd.cmd.zbc.entry_mask = ZBC_MASK(entries); + + pmu->pmu_pg.zbc_save_done = false; + + nvgpu_pmu_dbg(g, "cmd post ZBC_TABLE_UPDATE"); + err = nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_zbc_msg, pmu); + if (err != 0) { + nvgpu_err(g, "ZBC_TABLE_UPDATE cmd post failed"); + return; + } + pmu_wait_message_cond(pmu, nvgpu_get_poll_timeout(g), + &pmu->pmu_pg.zbc_save_done, 1); + if (!pmu->pmu_pg.zbc_save_done) { + nvgpu_err(g, "ZBC save timeout"); + } +} + +int gm20b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, + struct pmu_pg_stats_data *pg_stat_data) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct pmu_pg_stats stats; + int err; + + err = nvgpu_falcon_copy_from_dmem(&pmu->flcn, + pmu->pmu_pg.stat_dmem_offset[pg_engine_id], + (u8 *)&stats, (u32)sizeof(struct pmu_pg_stats), 0); + if (err != 0) { + nvgpu_err(g, "PMU falcon DMEM copy failed"); + return err; + } + + pg_stat_data->ingating_time = stats.pg_ingating_time_us; + pg_stat_data->ungating_time = stats.pg_ungating_time_us; + pg_stat_data->gating_cnt = stats.pg_gating_cnt; + pg_stat_data->avg_entry_latency_us = stats.pg_avg_entry_time_us; + pg_stat_data->avg_exit_latency_us = stats.pg_avg_exit_time_us; + + return err; +} diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.h b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.h new file mode 100644 index 000000000..c72811bc1 --- /dev/null +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_PG_SW_GM20B_H +#define NVGPU_PG_SW_GM20B_H + +#include + +struct gk20a; +struct pmu_pg_stats_data; + +#define ZBC_MASK(i) U16(~(~(0U) << ((i)+1U)) & 0xfffeU) + +u32 gm20b_pmu_pg_engines_list(struct gk20a *g); +u32 gm20b_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id); +void gm20b_pmu_save_zbc(struct gk20a *g, u32 entries); +int gm20b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, + struct pmu_pg_stats_data *pg_stat_data); + +#endif /* NVGPU_PG_SW_GM20B_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c index fb4e33f38..9ec74f6b0 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "pg_sw_gp106.h" @@ -126,3 +127,36 @@ u32 gp106_pmu_pg_engines_list(struct gk20a *g) return BIT32(PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | BIT32(PMU_PG_ELPG_ENGINE_ID_MS); } + +u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) +{ + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + return NVGPU_PMU_GR_FEATURE_MASK_RPPG; + } + + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { + return NVGPU_PMU_MS_FEATURE_MASK_ALL; + } + + return 0; +} + +bool gp106_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id) +{ + bool is_feature_supported = false; + + switch (feature_id) { + case PMU_PG_LPWR_FEATURE_RPPG: + is_feature_supported = nvgpu_lpwr_is_rppg_supported(g, + nvgpu_clk_arb_get_current_pstate(g)); + break; + case PMU_PG_LPWR_FEATURE_MSCG: + is_feature_supported = nvgpu_lpwr_is_mscg_supported(g, + nvgpu_clk_arb_get_current_pstate(g)); + break; + default: + is_feature_supported = false; + } + + return is_feature_supported; +} diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.h b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.h index b8200ad76..78a4109b4 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.h +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp106.h @@ -32,5 +32,7 @@ int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id); int gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data); u32 gp106_pmu_pg_engines_list(struct gk20a *g); +u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id); +bool gp106_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id); #endif /* NVGPU_PG_SW_GP106_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c index 3e19a0dbe..307607e66 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c @@ -359,58 +359,6 @@ bool gk20a_is_pmu_supported(struct gk20a *g) return true; } -u32 gk20a_pmu_pg_engines_list(struct gk20a *g) -{ - return BIT32(PMU_PG_ELPG_ENGINE_ID_GRAPHICS); -} - -u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) -{ - if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { - return NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; - } - - return 0; -} - -static void pmu_handle_zbc_msg(struct gk20a *g, struct pmu_msg *msg, - void *param, u32 status) -{ - struct nvgpu_pmu *pmu = param; - nvgpu_pmu_dbg(g, "reply ZBC_TABLE_UPDATE"); - pmu->pmu_pg.zbc_save_done = true; -} - -void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) -{ - struct nvgpu_pmu *pmu = &g->pmu; - struct pmu_cmd cmd; - size_t tmp_size; - - if (!pmu->pmu_ready || (entries == 0U) || !pmu->pmu_pg.zbc_ready) { - return; - } - - (void) memset(&cmd, 0, sizeof(struct pmu_cmd)); - cmd.hdr.unit_id = PMU_UNIT_PG; - tmp_size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_zbc_cmd); - nvgpu_assert(tmp_size <= (size_t)U8_MAX); - cmd.hdr.size = (u8)tmp_size; - cmd.cmd.zbc.cmd_type = g->pmu_ver_cmd_id_zbc_table_update; - cmd.cmd.zbc.entry_mask = ZBC_MASK(entries); - - pmu->pmu_pg.zbc_save_done = false; - - nvgpu_pmu_dbg(g, "cmd post ZBC_TABLE_UPDATE"); - nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_HPQ, - pmu_handle_zbc_msg, pmu); - pmu_wait_message_cond(pmu, nvgpu_get_poll_timeout(g), - &pmu->pmu_pg.zbc_save_done, 1); - if (!pmu->pmu_pg.zbc_save_done) { - nvgpu_err(g, "ZBC save timeout"); - } -} - int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu, struct nv_pmu_therm_msg *msg) { @@ -629,30 +577,6 @@ void gk20a_pmu_clear_idle_intr_status(struct gk20a *g) pwr_pmu_idle_intr_status_intr_f(1)); } -int gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, - struct pmu_pg_stats_data *pg_stat_data) -{ - struct nvgpu_pmu *pmu = &g->pmu; - struct pmu_pg_stats stats; - int err; - - err = nvgpu_falcon_copy_from_dmem(&pmu->flcn, - pmu->pmu_pg.stat_dmem_offset[pg_engine_id], - (u8 *)&stats, (u32)sizeof(struct pmu_pg_stats), 0); - if (err != 0) { - nvgpu_err(g, "PMU falcon DMEM copy failed"); - return err; - } - - pg_stat_data->ingating_time = stats.pg_ingating_time_us; - pg_stat_data->ungating_time = stats.pg_ungating_time_us; - pg_stat_data->gating_cnt = stats.pg_gating_cnt; - pg_stat_data->avg_entry_latency_us = stats.pg_avg_entry_time_us; - pg_stat_data->avg_exit_latency_us = stats.pg_avg_exit_time_us; - - return err; -} - u32 gk20a_pmu_falcon_base_addr(void) { return pwr_falcon_irqsset_r(); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h index 26fb04ad6..0cd3e288c 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h @@ -35,11 +35,6 @@ bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu); void gk20a_pmu_isr(struct gk20a *g); -u32 gk20a_pmu_pg_engines_list(struct gk20a *g); -u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id); - -void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); - void gk20a_pmu_init_perfmon_counter(struct gk20a *g); void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id); @@ -62,8 +57,6 @@ bool gk20a_is_pmu_supported(struct gk20a *g); int pmu_bootstrap(struct nvgpu_pmu *pmu); void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); -int gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, - struct pmu_pg_stats_data *pg_stat_data); u32 gk20a_pmu_falcon_base_addr(void); bool gk20a_pmu_is_engine_in_reset(struct gk20a *g); int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c index 28766ad6a..adf23a476 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c @@ -22,11 +22,7 @@ #include #include -#include -#include #include -#include -#include #include "pmu_gk20a.h" #include "pmu_gp106.h" @@ -71,39 +67,6 @@ int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset) return 0; } -u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) -{ - if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { - return NVGPU_PMU_GR_FEATURE_MASK_RPPG; - } - - if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { - return NVGPU_PMU_MS_FEATURE_MASK_ALL; - } - - return 0; -} - -bool gp106_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id) -{ - bool is_feature_supported = false; - - switch (feature_id) { - case PMU_PG_LPWR_FEATURE_RPPG: - is_feature_supported = nvgpu_lpwr_is_rppg_supported(g, - nvgpu_clk_arb_get_current_pstate(g)); - break; - case PMU_PG_LPWR_FEATURE_MSCG: - is_feature_supported = nvgpu_lpwr_is_mscg_supported(g, - nvgpu_clk_arb_get_current_pstate(g)); - break; - default: - is_feature_supported = false; - } - - return is_feature_supported; -} - void gp106_pmu_setup_apertures(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h index 865788f5f..542b0488a 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h @@ -28,8 +28,6 @@ struct gk20a; bool gp106_is_pmu_supported(struct gk20a *g); -u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id); -bool gp106_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id); bool gp106_pmu_is_engine_in_reset(struct gk20a *g); int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index fc7b7b3ad..639442de0 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -93,6 +93,7 @@ #include "common/sync/sema_cmdbuf_gk20a.h" #include "common/fifo/channel_gk20a.h" #include "common/fifo/channel_gm20b.h" +#include "common/pmu/pg/pg_sw_gm20b.h" #include "gk20a/ce2_gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -855,13 +856,13 @@ static const struct gpu_ops gm20b_ops = { .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, .pmu_enable_irq = gk20a_pmu_enable_irq, .write_dmatrfbase = gm20b_write_dmatrfbase, - .pmu_elpg_statistics = gk20a_pmu_elpg_statistics, + .pmu_elpg_statistics = gm20b_pmu_elpg_statistics, .pmu_init_perfmon = nvgpu_pmu_init_perfmon, .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, .pmu_pg_init_param = NULL, - .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, - .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list, .pmu_is_lpwr_feature_supported = NULL, .pmu_lpwr_enable_pg = NULL, .pmu_lpwr_disable_pg = NULL, @@ -871,7 +872,7 @@ static const struct gpu_ops gm20b_ops = { .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, .get_irqdest = gk20a_pmu_get_irqdest, .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, - .save_zbc = gk20a_pmu_save_zbc, + .save_zbc = gm20b_pmu_save_zbc, .pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status, }, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a4947f91b..205c17e47 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -109,6 +109,7 @@ #include "common/pmu/pmu_gk20a.h" #include "common/pmu/pmu_gm20b.h" #include "common/pmu/pmu_gp10b.h" +#include "common/pmu/pg/pg_sw_gm20b.h" #include "common/pmu/pg/pg_sw_gp10b.h" #include "common/top/top_gm20b.h" #include "common/top/top_gp10b.h" @@ -961,14 +962,14 @@ static const struct gpu_ops gp10b_ops = { .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, .pmu_pg_init_param = gp10b_pg_gr_init, - .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, - .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list, .dump_secure_fuses = pmu_dump_security_fuses_gm20b, .reset_engine = gk20a_pmu_engine_reset, .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, .get_irqdest = gk20a_pmu_get_irqdest, .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, - .save_zbc = gk20a_pmu_save_zbc, + .save_zbc = gm20b_pmu_save_zbc, .pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status, }, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 062a022e8..07a2e76f6 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -114,7 +114,6 @@ #include "common/pmu/pmu_gp10b.h" #include "common/pmu/pmu_gp106.h" #include "common/pmu/pmu_gv11b.h" -#include "common/pmu/pg/pg_sw_gp106.h" #include "common/nvlink/init/device_reginit_gv100.h" #include "common/nvlink/intr_and_err_handling_gv100.h" #include "hal/nvlink/minion_gv100.h" @@ -1130,23 +1129,17 @@ static const struct gpu_ops gv100_ops = { .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, .pmu_enable_irq = gk20a_pmu_enable_irq, .is_pmu_supported = gp106_is_pmu_supported, - .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, - .pmu_elpg_statistics = gp106_pmu_elpg_statistics, .pmu_init_perfmon = nvgpu_pmu_init_perfmon, .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, .pmu_mutex_owner = gk20a_pmu_mutex_owner, .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, - .pmu_is_lpwr_feature_supported = - gp106_pmu_is_lpwr_feature_supported, .pmu_msgq_tail = gk20a_pmu_msgq_tail, - .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, .pmu_reset = nvgpu_pmu_reset, .pmu_queue_head = gk20a_pmu_queue_head, .pmu_pg_param_post_init = nvgpu_lpwr_post_init, .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, - .pmu_pg_init_param = gp106_pg_param_init, .reset_engine = gp106_pmu_engine_reset, .write_dmatrfbase = gp10b_write_dmatrfbase, .pmu_mutex_size = pwr_pmu_mutex__size_1_v, @@ -1156,7 +1149,6 @@ static const struct gpu_ops gv100_ops = { .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, .setup_apertures = gp106_pmu_setup_apertures, .secured_pmu_start = gm20b_secured_pmu_start, - .save_zbc = gk20a_pmu_save_zbc, .pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status, }, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e5ed9bc32..31f566fff 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -110,6 +110,7 @@ #include "common/pmu/pmu_gp10b.h" #include "common/pmu/pmu_gp106.h" #include "common/pmu/pmu_gv11b.h" +#include "common/pmu/pg/pg_sw_gm20b.h" #include "common/pmu/pg/pg_sw_gp106.h" #include "common/pmu/pg/pg_sw_gv11b.h" #include "common/top/top_gm20b.h" @@ -1120,8 +1121,8 @@ static const struct gpu_ops gv11b_ops = { .pmu_pg_init_param = gv11b_pg_gr_init, .pmu_setup_elpg = gv11b_pmu_setup_elpg, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, - .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, - .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list, .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, .pmu_elpg_statistics = gp106_pmu_elpg_statistics, .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, @@ -1139,7 +1140,7 @@ static const struct gpu_ops gv11b_ops = { .dump_secure_fuses = pmu_dump_security_fuses_gm20b, .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, /* PMU uocde */ - .save_zbc = gk20a_pmu_save_zbc, + .save_zbc = gm20b_pmu_save_zbc, .pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status, #endif diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 9e66ad652..ae71d2c38 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -119,7 +119,6 @@ #include "common/pmu/pmu_gp106.h" #include "common/pmu/pmu_gv11b.h" #include "common/pmu/pmu_tu104.h" -#include "common/pmu/pg/pg_sw_gp106.h" #include "common/top/top_gm20b.h" #include "common/top/top_gp10b.h" #include "common/top/top_gv100.h" @@ -1168,23 +1167,17 @@ static const struct gpu_ops tu104_ops = { .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, .pmu_enable_irq = gk20a_pmu_enable_irq, .is_pmu_supported = tu104_is_pmu_supported, - .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, - .pmu_elpg_statistics = gp106_pmu_elpg_statistics, .pmu_init_perfmon = nvgpu_pmu_init_perfmon, .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, .pmu_mutex_owner = gk20a_pmu_mutex_owner, .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, - .pmu_is_lpwr_feature_supported = - gp106_pmu_is_lpwr_feature_supported, .pmu_msgq_tail = gk20a_pmu_msgq_tail, - .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, .pmu_reset = nvgpu_pmu_reset, .pmu_queue_head = gk20a_pmu_queue_head, .pmu_pg_param_post_init = nvgpu_lpwr_post_init, .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, - .pmu_pg_init_param = gp106_pg_param_init, .reset_engine = gp106_pmu_engine_reset, .write_dmatrfbase = gp10b_write_dmatrfbase, .pmu_mutex_size = pwr_pmu_mutex__size_1_v, @@ -1195,7 +1188,6 @@ static const struct gpu_ops tu104_ops = { .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, .setup_apertures = gp106_pmu_setup_apertures, .secured_pmu_start = gm20b_secured_pmu_start, - .save_zbc = gk20a_pmu_save_zbc, .pmu_clear_bar0_host_err_status = gm20b_clear_pmu_bar0_host_err_status, },