diff --git a/drivers/gpu/nvgpu/common/therm/therm_gp106.c b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
index 33c81ca01..8ee39bc2a 100644
--- a/drivers/gpu/nvgpu/common/therm/therm_gp106.c
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
@@ -51,6 +51,8 @@ int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
 	} else if ((therm_temp_sensor_tsense_state_v(readval) &
 		   therm_temp_sensor_tsense_state_shadow_v()) != 0U) {
 		nvgpu_err(g, "Reading temperature from SHADOWed sensor!");
+	} else {
+		nvgpu_log_info(g, "Finished reading temperature");
 	}
 
 	// Convert from F9.5 -> F27.5 -> F24.8.
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 4489c4e43..2eb5117e1 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -1347,6 +1347,8 @@ long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate,
 		freq = gpc_pll_params.max_freq;
 	} else if (freq < gpc_pll_params.min_freq) {
 		freq = gpc_pll_params.min_freq;
+	} else {
+		nvgpu_log_info(g, "frequency within range");
 	}
 
 	tmp_pll = clk->gpc_pll;
@@ -1417,6 +1419,8 @@ static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq)
 		freq = gpc_pll_params.max_freq;
 	} else if (freq < gpc_pll_params.min_freq) {
 		freq = gpc_pll_params.min_freq;
+	} else {
+		nvgpu_log_info(g, "frequency within range");
 	}
 
 	if (freq != old_freq) {
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index b28486da9..65c75dd33 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -47,7 +47,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 	if ((msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_SET_OBJECT) &&
 		(msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_QUERY) &&
 		(msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_LOAD)) {
-		nvgpu_err(g, "unknow msg %x", msg->msg.pmgr.msg_type);
+		nvgpu_err(g, "unknown msg %x", msg->msg.pmgr.msg_type);
 		return;
 	}
 
@@ -80,6 +80,9 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 				msg->msg.pmgr.load.flcnstatus);
 			return;
 		}
+	} else {
+		/*Will not hit this case due to check in the beginning itself*/
+		nvgpu_err(g, "unknown msg %x", msg->msg.pmgr.msg_type);
 	}
 
 	phandlerparams->success = 1;