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gpu: nvgpu: report gpc_tpc_mask in physical order

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At present, there is an inconsistency in the order in which
gpc_tpc masks are reported to the userspace. Both gpc and
tpc masks are reported using physical-ids. However, the
gpc_tpc_masks array is ordered by logical gpc-ids and
not physical-ids. This creates a mismatch between the gpc
reported as enabled in the gpc_mask and its corresponding
gpc_tpc_mask.

Introduce field "gpc_tpc_mask_physical" which stores the
gpc_tpc_masks in physical order and update
NVGPU_GPU_IOCTL_GET_TPC_MASKS to return this field.

Bug 200665942

Change-Id: I63aa83414a59676b7e7d36b6deb527e2f3c04cff
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2531114
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2021-05-18 11:01:58 +00:00
committed by mobile promotions
parent 842bef7124
commit f80dccb543
6 changed files with 80 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/nvgpu/include/nvgpu/gr/config.h
View File

@@ -238,7 +238,21 @@ u32 nvgpu_gr_config_get_pes_tpc_count(struct nvgpu_gr_config *config,
u32 *nvgpu_gr_config_get_base_mask_gpc_tpc(struct nvgpu_gr_config *config);
/**
* @brief Get TPC mask for given GPC.
* @brief Get base address of array that stores mask of TPCs in GPC.
*
* @param config [in] Pointer to GR configuration struct.
*
* Get base address of array that stores mask of TPCs in GPC, ordered
* in physical-id when in non-MIG(legacy) mode and by logical-id when in
* MIG mode.
*
* @return base address of array that stores mask of TPCs in GPC.
*/
u32 *nvgpu_gr_config_get_gpc_tpc_mask_physical_base(
struct nvgpu_gr_config *config);
/**
* @brief Get TPC mask for given logical GPC index.
*
* @param config [in] Pointer to GR configuration struct.
* @param gpc_index [in] Valid GPC index.
@@ -247,13 +261,31 @@ u32 *nvgpu_gr_config_get_base_mask_gpc_tpc(struct nvgpu_gr_config *config);
* Each set bit indicates TPC with that index is available, otherwise
* the TPC is considered floorswept.
* GPC index must be less than value returned by
* #nvgpu_gr_config_get_gpc_count(), otherwise an assert is raised.
* #nvgpu_gr_config_get_max_gpc_count(), otherwise an assert is raised.
*
* @return mask of TPCs for given GPC.
*/
u32 nvgpu_gr_config_get_gpc_tpc_mask(struct nvgpu_gr_config *config,
u32 gpc_index);
/**
* @brief Get TPC mask for given physical GPC index.
*
* @param config [in] Pointer to GR configuration struct.
* @param gpc_index [in] Valid GPC physical id.
*
* This function returns mask of TPCs for given GPC index, which will be
* the physical-id in non-MIG(legacy) mode and logical-id in MIG mode.
* Each set bit indicates TPC with that index is available, otherwise
* the TPC is considered floorswept.
* GPC index must be less than value returned by
* #nvgpu_gr_config_get_max_gpc_count(), otherwise an assert is raised.
*
* @return mask of TPCs for given GPC.
*/
u32 nvgpu_gr_config_get_gpc_tpc_mask_physical(struct nvgpu_gr_config *config,
u32 gpc_index);
/**
* @brief Set TPC mask for given GPC.
*

1
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
View File

@@ -483,6 +483,7 @@ struct tegra_vgpu_constants_params {
* TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC
*/
u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT];
u16 gpc_tpc_mask_physical[TEGRA_VGPU_MAX_GPC_COUNT];
u16 gpc_ppc_count[TEGRA_VGPU_MAX_GPC_COUNT];
u32 pes_tpc_count[TEGRA_VGPU_MAX_PES_COUNT_PER_GPC
* TEGRA_VGPU_MAX_GPC_COUNT];