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gpu: nvgpu: cleanup idle_wait and wait_empty APIs

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All cases where the wait_empty HAL API and the wait_idle, wait_fe_idle
APIs were being called used the same parameters, so move those
parameters inside the APIs.

JIRA NVGPU-1008

Change-Id: Ib864260f5a4c6458d81b7d2326076c0bd9c4b5af
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-01-07 16:23:13 -05:00
committed by mobile promotions
parent 4ba92354c0
commit f910525e14
8 changed files with 42 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

65
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -224,10 +224,9 @@ static void gr_gk20a_load_falcon_imem(struct gk20a *g)
}
}
int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay)
int gr_gk20a_wait_idle(struct gk20a *g)
{
u32 delay = expect_delay;
u32 delay = GR_IDLE_CHECK_DEFAULT;
bool ctxsw_active;
bool gr_busy;
u32 gr_engine_id;
@@ -239,7 +238,8 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER);
nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
NVGPU_TIMER_CPU_TIMER);
do {
/* fmodel: host gets fifo_engine_status(gr) from gr
@@ -276,11 +276,10 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
return -EAGAIN;
}
int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay)
int gr_gk20a_wait_fe_idle(struct gk20a *g)
{
u32 val;
u32 delay = expect_delay;
u32 delay = GR_IDLE_CHECK_DEFAULT;
struct nvgpu_timeout timeout;
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
@@ -289,7 +288,8 @@ int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms,
nvgpu_log_fn(g, " ");
nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER);
nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
NVGPU_TIMER_CPU_TIMER);
do {
val = gk20a_readl(g, gr_status_r());
@@ -1218,16 +1218,13 @@ int gk20a_init_sw_bundle(struct gk20a *g)
if (gr_pipe_bundle_address_value_v(sw_bundle_init->l[i].addr) ==
GR_GO_IDLE_BUNDLE) {
err = gr_gk20a_wait_idle(g,
gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
if (err != 0) {
goto error;
}
}
err = gr_gk20a_wait_fe_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_fe_idle(g);
if (err != 0) {
goto error;
}
@@ -1251,8 +1248,7 @@ int gk20a_init_sw_bundle(struct gk20a *g)
gk20a_writel(g, gr_pipe_bundle_config_r(),
gr_pipe_bundle_config_override_pipe_mode_disabled_f());
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
/* restore fe_go_idle */
gk20a_writel(g, gr_fe_go_idle_timeout_r(),
@@ -1373,8 +1369,7 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
goto clean_up;
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
/* load ctx init */
for (i = 0; i < sw_ctx_load->count; i++) {
@@ -1390,8 +1385,7 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
if (err != 0) {
goto clean_up;
}
@@ -1414,8 +1408,7 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
goto clean_up;
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
if (err != 0) {
goto restore_fe_go_idle;
}
@@ -1430,8 +1423,7 @@ restore_fe_go_idle:
gk20a_writel(g, gr_fe_go_idle_timeout_r(),
gr_fe_go_idle_timeout_count_prod_f());
if ((err != 0) || (gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT) != 0)) {
if ((err != 0) || (gr_gk20a_wait_idle(g) != 0)) {
goto clean_up;
}
@@ -1455,8 +1447,7 @@ restore_fe_go_idle:
sw_method_init->l[i].addr);
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
if (err != 0) {
goto clean_up;
}
@@ -3222,8 +3213,7 @@ void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
return;
}
ret = g->ops.gr.wait_empty(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
ret = g->ops.gr.wait_empty(g);
if (ret != 0) {
nvgpu_err(g,
"failed to idle graphics");
@@ -3566,8 +3556,7 @@ int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
return ret;
}
ret = g->ops.gr.wait_empty(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
ret = g->ops.gr.wait_empty(g);
if (ret != 0) {
nvgpu_err(g,
"failed to idle graphics");
@@ -3953,8 +3942,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
sw_ctx_load->l[i].value);
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
if (err != 0U) {
goto out;
}
@@ -3979,8 +3967,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
goto out;
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
if (err != 0U) {
goto restore_fe_go_idle;
}
@@ -3990,8 +3977,7 @@ restore_fe_go_idle:
gk20a_writel(g, gr_fe_go_idle_timeout_r(),
gr_fe_go_idle_timeout_count_prod_f());
if ((err != 0U) || (gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT) != 0)) {
if ((err != 0U) || (gr_gk20a_wait_idle(g) != 0)) {
goto out;
}
@@ -4015,8 +4001,7 @@ restore_fe_go_idle:
sw_method_init->l[i].addr);
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
out:
nvgpu_log_fn(g, "done");
return err;
@@ -4177,8 +4162,7 @@ static int gk20a_init_gr_reset_enable_hw(struct gk20a *g)
goto out;
}
err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
if (err != 0U) {
goto out;
}
@@ -5733,8 +5717,7 @@ int gk20a_gr_suspend(struct gk20a *g)
nvgpu_log_fn(g, " ");
ret = g->ops.gr.wait_empty(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
ret = g->ops.gr.wait_empty(g);
if (ret != 0U) {
return ret;
}

6
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -596,8 +596,7 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val);
void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay);
int gr_gk20a_wait_idle(struct gk20a *g);
int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr);
@@ -655,8 +654,7 @@ u32 gr_gk20a_get_ctx_id(struct gk20a *g, struct nvgpu_mem *ctx_mem);
u32 gk20a_gr_get_sm_hww_warp_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm);
u32 gk20a_gr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm);
int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay);
int gr_gk20a_wait_fe_idle(struct gk20a *g);
struct dbg_session_gk20a;

8
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -1310,10 +1310,9 @@ static bool gr_activity_empty_or_preempted(u32 val)
return true;
}
int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay)
int gr_gp10b_wait_empty(struct gk20a *g)
{
u32 delay = expect_delay;
u32 delay = GR_IDLE_CHECK_DEFAULT;
bool ctxsw_active;
bool gr_busy;
u32 gr_status;
@@ -1322,7 +1321,8 @@ int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
nvgpu_log_fn(g, " ");
nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER);
nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
NVGPU_TIMER_CPU_TIMER);
do {
/* fmodel: host gets fifo_engine_status(gr) from gr

3
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -105,8 +105,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_mem *ctxheader);
int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o);
int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay);
int gr_gp10b_wait_empty(struct gk20a *g);
void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,
u64 addr, bool patch);

15
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -2124,10 +2124,9 @@ static bool gr_activity_empty_or_preempted(u32 val)
return true;
}
int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay)
int gr_gv11b_wait_empty(struct gk20a *g)
{
u32 delay = expect_delay;
u32 delay = GR_IDLE_CHECK_DEFAULT;
bool ctxsw_active;
bool gr_busy;
u32 gr_status;
@@ -2136,7 +2135,8 @@ int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms,
nvgpu_log_fn(g, " ");
nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER);
nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
NVGPU_TIMER_CPU_TIMER);
do {
/* fmodel: host gets fifo_engine_status(gr) from gr
@@ -2801,8 +2801,7 @@ static int gv11b_write_bundle_veid_state(struct gk20a *g, u32 index)
sw_veid_bundle_init->l[index].addr |
gr_pipe_bundle_address_veid_f(j));
err = gr_gk20a_wait_fe_idle(g, gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_fe_idle(g);
}
return err;
}
@@ -2832,9 +2831,7 @@ int gr_gv11b_init_sw_veid_bundle(struct gk20a *g)
nvgpu_log_fn(g, "go idle bundle");
gk20a_writel(g, gr_pipe_bundle_address_r(),
sw_veid_bundle_init->l[i].addr);
err = gr_gk20a_wait_idle(g,
gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
} else {
err = gv11b_write_bundle_veid_state(g, i);
}

5
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -1,7 +1,7 @@
/*
* GV11B GPU GR
*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -128,8 +128,7 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data);
int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o);
int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay);
int gr_gv11b_wait_empty(struct gk20a *g);
void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,
u64 addr, bool patch);

3
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -371,8 +371,7 @@ struct gpu_ops {
u32* (*get_rop_l2_en_mask)(struct gk20a *g);
void (*init_sm_dsm_reg_info)(void);
void (*init_ovr_sm_dsm_perf)(void);
int (*wait_empty)(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay);
int (*wait_empty)(struct gk20a *g);
void (*init_cyclestats)(struct gk20a *g);
int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch,
u64 sms, bool enable);

8
drivers/gpu/nvgpu/tu104/gr_tu104.c
View File

@@ -110,13 +110,9 @@ int gr_tu104_init_sw_bundle64(struct gk20a *g)
if (gr_pipe_bundle_address_value_v(sw_bundle64_init->l[i].addr)
== GR_GO_IDLE_BUNDLE) {
err = gr_gk20a_wait_idle(g,
gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_idle(g);
} else if (nvgpu_platform_is_silicon(g)) {
err = gr_gk20a_wait_fe_idle(g,
gk20a_get_gr_idle_timeout(g),
GR_IDLE_CHECK_DEFAULT);
err = gr_gk20a_wait_fe_idle(g);
}
if (err != 0) {
break;