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gpu: nvgpu: gp10b: enhance priv error reporting
-Append 0x for info dumped in hex format -Dump subid and priv_level for ERROR_INFO -Decode ERROR_CODE for supported error types Bug 2072157 Bug 200392445 Bug 2055510 Bug 200379815 Change-Id: I78df8ca15421ee37631157082648e9b545367c95 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1672292 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Seema Khowala
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@@ -1,7 +1,7 @@
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/*
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* GP10B priv ring
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*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -33,6 +33,69 @@
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#include <nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h>
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static const char * const invalid_str = "invalid";
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static const char *const error_type_badf1xyy[] = {
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"client timeout",
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"decode error",
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"client in reset",
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"client floorswept",
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"client stuck ack",
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"client expected ack",
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"fence error",
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"subid error",
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"byte access unsupported",
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};
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static const char *const error_type_badf2xyy[] = {
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"orphan gpc/fbp"
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};
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static const char *const error_type_badf3xyy[] = {
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"priv ring dead"
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};
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static const char *const error_type_badf5xyy[] = {
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"client error",
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"priv level violation",
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"indirect priv level violation",
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"local local ring error",
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"falcon mem access priv level violation",
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"pri route error"
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};
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static void gp10b_priv_ring_decode_error_code(struct gk20a *g,
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u32 error_code)
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{
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u32 error_type, error_type_index;
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error_type = (error_code & 0x0000f000) >> 24;
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error_type_index = (error_code & 0x00000f00) >> 16;
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error_code = error_code & 0xBADFf000;
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if (error_code == 0xBADF1000) {
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if (error_type_index <
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ARRAY_SIZE(error_type_badf1xyy))
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nvgpu_err(g, "%s",
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error_type_badf1xyy[error_type_index]);
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} else if (error_code == 0xBADF2000) {
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if (error_type_index <
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ARRAY_SIZE(error_type_badf2xyy))
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nvgpu_err(g, "%s",
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error_type_badf2xyy[error_type_index]);
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} else if (error_code == 0xBADF3000) {
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if (error_type_index <
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ARRAY_SIZE(error_type_badf3xyy))
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nvgpu_err(g, "%s",
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error_type_badf3xyy[error_type_index]);
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} else if (error_code == 0xBADF5000) {
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if (error_type_index <
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ARRAY_SIZE(error_type_badf5xyy))
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nvgpu_err(g, "%s",
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error_type_badf5xyy[error_type_index]);
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}
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}
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void gp10b_priv_ring_isr(struct gk20a *g)
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{
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u32 status0, status1;
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@@ -40,6 +103,8 @@ void gp10b_priv_ring_isr(struct gk20a *g)
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s32 retry = 100;
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u32 gpc;
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u32 gpc_stride, offset;
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u32 error_info;
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u32 error_code;
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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nvgpu_info(g, "unhandled priv ring intr");
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@@ -63,11 +128,20 @@ void gp10b_priv_ring_isr(struct gk20a *g)
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nvgpu_err(g, "ring overflowed");
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if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
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nvgpu_err(g, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
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error_info =
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gk20a_readl(g, pri_ringstation_sys_priv_error_info_r());
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error_code =
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gk20a_readl(g, pri_ringstation_sys_priv_error_code_r());
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nvgpu_err(g, "SYS write error. ADR 0x%08x WRDAT 0x%08x "
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"INFO 0x%08x (subid 0x%08x priv level %d), "
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"CODE 0x%08x",
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gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
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error_info,
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pri_ringstation_sys_priv_error_info_subid_v(error_info),
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pri_ringstation_sys_priv_error_info_priv_level_v(error_info),
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error_code);
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gp10b_priv_ring_decode_error_code(g, error_code);
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}
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if (status1) {
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@@ -75,16 +149,25 @@ void gp10b_priv_ring_isr(struct gk20a *g)
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for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
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offset = gpc * gpc_stride;
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if (status1 & BIT(gpc)) {
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nvgpu_err(g, "GPC%u write error. ADR %08x "
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"WRDAT %08x INFO %08x, CODE %08x", gpc,
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error_info = gk20a_readl(g,
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pri_ringstation_gpc_gpc0_priv_error_info_r() + offset);
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error_code = gk20a_readl(g,
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pri_ringstation_gpc_gpc0_priv_error_code_r() + offset);
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nvgpu_err(g, "GPC%u write error. ADR 0x%08x "
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"WRDAT 0x%08x "
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"INFO 0x%08x (subid 0x%08x priv level %d), "
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"CODE 0x%08x", gpc,
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gk20a_readl(g,
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pri_ringstation_gpc_gpc0_priv_error_adr_r() + offset),
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gk20a_readl(g,
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pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + offset),
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gk20a_readl(g,
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pri_ringstation_gpc_gpc0_priv_error_info_r() + offset),
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gk20a_readl(g,
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pri_ringstation_gpc_gpc0_priv_error_code_r() + offset));
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error_info,
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pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info),
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pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info),
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error_code);
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gp10b_priv_ring_decode_error_code(g, error_code);
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status1 = status1 & (~(BIT(gpc)));
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if (!status1)
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break;
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -72,6 +72,14 @@ static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
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{
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return 0x00128128U;
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}
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static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_subid_v(u32 r)
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{
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return (r >> 24U) & 0x3fU;
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}
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static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(u32 r)
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{
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return (r >> 20U) & 0x3U;
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}
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static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
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{
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return 0x0012812cU;
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -84,6 +84,14 @@ static inline u32 pri_ringstation_sys_priv_error_info_r(void)
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{
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return 0x00122128U;
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}
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static inline u32 pri_ringstation_sys_priv_error_info_subid_v(u32 r)
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{
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return (r >> 24U) & 0x3fU;
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}
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static inline u32 pri_ringstation_sys_priv_error_info_priv_level_v(u32 r)
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{
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return (r >> 20U) & 0x3U;
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}
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static inline u32 pri_ringstation_sys_priv_error_code_r(void)
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{
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return 0x0012212cU;
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