From f9cac0c64df6ab8b6300f36e231a57a3921bd7ae Mon Sep 17 00:00:00 2001 From: Antony Clince Alex Date: Sat, 19 Jun 2021 10:17:51 +0000 Subject: [PATCH] gpu: nvgpu: remove nvgpu_next files Remove all nvgpu_next files and move the code into corresponding nvgpu files. Merge nvgpu-next-*.yaml into nvgpu-.yaml files. Jira NVGPU-4771 Change-Id: I595311be3c7bbb4f6314811e68712ff01763801e Signed-off-by: Antony Clince Alex Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547557 Reviewed-by: svc_kernel_abi Reviewed-by: Mahantesh Kumbar Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- arch/nvgpu-common.yaml | 19 +- arch/nvgpu-gpu_hw.yaml | 73 ++- arch/nvgpu-hal-new.yaml | 319 +++++++++++-- arch/nvgpu-hal-vgpu.yaml | 4 +- arch/nvgpu-linux.yaml | 5 +- arch/nvgpu-next-common.yaml | 180 ------- arch/nvgpu-next-gpu_hw.yaml | 98 ---- arch/nvgpu-next-hal-vgpu.yaml | 30 -- arch/nvgpu-next-hal.yaml | 427 ----------------- arch/nvgpu-next-linux.yaml | 41 -- arch/nvgpu.yaml | 10 +- drivers/gpu/nvgpu/Makefile | 14 +- drivers/gpu/nvgpu/Makefile.sources | 11 - drivers/gpu/nvgpu/common/acr/acr_bootstrap.c | 136 ++++++ drivers/gpu/nvgpu/common/acr/acr_bootstrap.h | 9 +- .../common/acr/nvgpu_next_acr_bootstrap.c | 167 ------- .../common/acr/nvgpu_next_acr_bootstrap.h | 32 -- drivers/gpu/nvgpu/common/cic/cic.c | 69 +++ drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c | 92 ---- drivers/gpu/nvgpu/common/fb/fb.c | 24 +- drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c | 44 -- drivers/gpu/nvgpu/common/fifo/engines.c | 55 +++ .../nvgpu/common/fifo/nvgpu_next_engines.c | 79 ---- .../nvgpu/common/fifo/nvgpu_next_runlist.c | 113 ----- drivers/gpu/nvgpu/common/fifo/runlist.c | 90 ++++ drivers/gpu/nvgpu/common/gr/fs_state.c | 32 ++ drivers/gpu/nvgpu/common/gr/gr.c | 60 ++- .../gpu/nvgpu/common/gr/nvgpu_next_fs_state.c | 57 --- drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c | 81 ---- drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c | 92 ---- drivers/gpu/nvgpu/common/netlist/netlist.c | 332 ++++++++++++- .../gpu/nvgpu/common/netlist/netlist_priv.h | 55 ++- .../nvgpu/common/netlist/nvgpu_next_netlist.c | 383 --------------- .../common/netlist/nvgpu_next_netlist_priv.h | 92 ---- .../common/profiler/nvgpu_next_profiler.c | 38 -- .../common/profiler/nvgpu_next_profiler.h | 28 -- drivers/gpu/nvgpu/common/profiler/profiler.c | 15 + drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c | 61 --- .../nvgpu/common/sim/nvgpu_next_sim_netlist.c | 445 ------------------ drivers/gpu/nvgpu/common/sim/sim.c | 37 ++ drivers/gpu/nvgpu/common/sim/sim_netlist.c | 424 ++++++++++++++++- drivers/gpu/nvgpu/hal/class/class_ga100.c | 3 +- drivers/gpu/nvgpu/hal/class/class_ga10b.c | 3 +- drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c | 1 - .../nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c | 3 +- .../nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c | 3 +- drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c | 1 - drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c | 2 - .../power_features/cg/ga100_gating_reglist.c | 1 - .../power_features/cg/ga10b_gating_reglist.c | 1 - drivers/gpu/nvgpu/include/nvgpu/cic.h | 64 ++- drivers/gpu/nvgpu/include/nvgpu/class.h | 12 +- drivers/gpu/nvgpu/include/nvgpu/device.h | 37 +- drivers/gpu/nvgpu/include/nvgpu/ecc.h | 18 +- .../gpu/nvgpu/include/nvgpu/engine_status.h | 15 +- drivers/gpu/nvgpu/include/nvgpu/engines.h | 8 +- drivers/gpu/nvgpu/include/nvgpu/errata.h | 9 +- drivers/gpu/nvgpu/include/nvgpu/fb.h | 39 +- drivers/gpu/nvgpu/include/nvgpu/fuse.h | 38 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 5 + drivers/gpu/nvgpu/include/nvgpu/gops/ce.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gops/cg.h | 15 +- .../gpu/nvgpu/include/nvgpu/gops/debugger.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/gops/fb.h | 45 +- drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h | 7 +- drivers/gpu/nvgpu/include/nvgpu/gops/gr.h | 28 +- drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h | 12 +- drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h | 6 +- drivers/gpu/nvgpu/include/nvgpu/gops/mc.h | 31 +- drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h | 6 +- drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h | 2 +- .../gpu/nvgpu/include/nvgpu/gops/priv_ring.h | 6 +- .../gpu/nvgpu/include/nvgpu/gops/runlist.h | 10 +- drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gr/gr.h | 4 +- .../include/nvgpu/gr/nvgpu_next_fs_state.h | 31 -- .../nvgpu/include/nvgpu/gr/nvgpu_next_gr.h | 37 -- .../include/nvgpu/gr/nvgpu_next_gr_ecc.h | 30 -- drivers/gpu/nvgpu/include/nvgpu/mc.h | 43 +- drivers/gpu/nvgpu/include/nvgpu/mm.h | 3 +- drivers/gpu/nvgpu/include/nvgpu/netlist.h | 60 ++- drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h | 9 +- .../gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h | 95 ---- .../nvgpu/include/nvgpu/nvgpu_next_class.h | 36 -- .../nvgpu/include/nvgpu/nvgpu_next_device.h | 58 --- .../gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h | 38 -- .../include/nvgpu/nvgpu_next_engine_status.h | 37 -- .../nvgpu/include/nvgpu/nvgpu_next_engines.h | 41 -- .../gpu/nvgpu/include/nvgpu/nvgpu_next_err.h | 32 -- .../nvgpu/include/nvgpu/nvgpu_next_errata.h | 35 -- .../gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h | 65 --- .../gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h | 71 --- .../nvgpu/include/nvgpu/nvgpu_next_gops_ce.h | 29 -- .../nvgpu/include/nvgpu/nvgpu_next_gops_cg.h | 42 -- .../nvgpu/include/nvgpu/nvgpu_next_gops_fb.h | 36 -- .../include/nvgpu/nvgpu_next_gops_fb_vab.h | 61 --- .../include/nvgpu/nvgpu_next_gops_fifo.h | 29 -- .../include/nvgpu/nvgpu_next_gops_fuse.h | 34 -- .../nvgpu/include/nvgpu/nvgpu_next_gops_gr.h | 29 -- .../nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h | 41 -- .../include/nvgpu/nvgpu_next_gops_gr_init.h | 33 -- .../include/nvgpu/nvgpu_next_gops_gr_intr.h | 29 -- .../include/nvgpu/nvgpu_next_gops_grmgr.h | 37 -- .../nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h | 28 -- .../include/nvgpu/nvgpu_next_gops_ltc_intr.h | 29 -- .../nvgpu/include/nvgpu/nvgpu_next_gops_mc.h | 60 --- .../include/nvgpu/nvgpu_next_gops_pbdma.h | 33 -- .../include/nvgpu/nvgpu_next_gops_perf.h | 30 -- .../include/nvgpu/nvgpu_next_gops_priv_ring.h | 32 -- .../include/nvgpu/nvgpu_next_gops_runlist.h | 37 -- .../nvgpu/include/nvgpu/nvgpu_next_litter.h | 36 -- .../gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h | 69 --- .../gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h | 29 -- .../nvgpu/include/nvgpu/nvgpu_next_netlist.h | 90 ---- .../nvgpu/include/nvgpu/nvgpu_next_pbdma.h | 44 -- .../nvgpu/include/nvgpu/nvgpu_next_runlist.h | 52 -- .../gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h | 42 -- drivers/gpu/nvgpu/include/nvgpu/pbdma.h | 13 +- drivers/gpu/nvgpu/include/nvgpu/profiler.h | 4 + drivers/gpu/nvgpu/include/nvgpu/runlist.h | 37 +- drivers/gpu/nvgpu/include/nvgpu/sim.h | 21 +- drivers/gpu/nvgpu/os/linux/ioctl_prof.c | 109 ++++- drivers/gpu/nvgpu/os/linux/ioctl_prof.h | 10 +- .../nvgpu/os/linux/nvgpu_next_ioctl_prof.c | 137 ------ .../nvgpu/os/linux/nvgpu_next_ioctl_prof.h | 24 - 126 files changed, 2351 insertions(+), 4554 deletions(-) delete mode 100644 arch/nvgpu-next-common.yaml delete mode 100644 arch/nvgpu-next-gpu_hw.yaml delete mode 100644 arch/nvgpu-next-hal-vgpu.yaml delete mode 100644 arch/nvgpu-next-hal.yaml delete mode 100644 arch/nvgpu-next-linux.yaml delete mode 100644 drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c delete mode 100644 drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h delete mode 100644 drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c delete mode 100644 drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c delete mode 100644 drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c delete mode 100644 drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c delete mode 100644 drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c delete mode 100644 drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c delete mode 100644 drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c delete mode 100644 drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c delete mode 100644 drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h delete mode 100644 drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c delete mode 100644 drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h delete mode 100644 drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c delete mode 100644 drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h delete mode 100644 drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c delete mode 100644 drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 165f9eea5..f7f816b3a 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -26,12 +26,15 @@ bios: common/vbios/bios_sw_gv100.h, common/vbios/bios_sw_tu104.c, common/vbios/bios_sw_tu104.h, + common/vbios/bios_sw_ga100.c, + common/vbios/bios_sw_ga100.h, common/vbios/nvlink_bios.c, include/nvgpu/bios.h, include/nvgpu/nvlink_bios.h, include/nvgpu/gops/bios.h, include/nvgpu/gops/xve.h ] + ce: safe: yes owner: Thomas F @@ -269,7 +272,9 @@ acr_fusa: common/acr/acr_sw_gv11b.h, common/acr/nvgpu_acr_interface.h, include/nvgpu/gops/acr.h, - include/nvgpu/acr.h ] + include/nvgpu/acr.h, + include/nvgpu/riscv.h, + common/riscv/riscv.c ] acr: safe: no @@ -281,7 +286,11 @@ acr: common/acr/acr_sw_gm20b.c, common/acr/acr_sw_gm20b.h, common/acr/acr_sw_tu104.c, - common/acr/acr_sw_tu104.h ] + common/acr/acr_sw_tu104.h, + common/acr/acr_sw_ga10b.c, + common/acr/acr_sw_ga10b.h, + common/acr/acr_sw_ga100.c, + common/acr/acr_sw_ga100.h ] sbr: safe: yes @@ -348,6 +357,8 @@ falcon: gpu: dgpu sources: [ common/falcon/falcon_sw_tu104.c, common/falcon/falcon_sw_tu104.h, + common/falcon/falcon_sw_ga10b.c, + common/falcon/falcon_sw_ga10b.h, include/nvgpu/gops/gsp.h, include/nvgpu/gops/nvdec.h ] deps: [ ] @@ -834,6 +845,8 @@ pmu: common/pmu/perfmon/pmu_perfmon_sw_gm20b.h, common/pmu/perfmon/pmu_perfmon_sw_gv11b.c, common/pmu/perfmon/pmu_perfmon_sw_gv11b.h, + common/pmu/perfmon/pmu_perfmon_sw_ga10b.c, + common/pmu/perfmon/pmu_perfmon_sw_ga10b.h, include/nvgpu/pmu/pmu_perfmon.h ] clk: @@ -900,6 +913,8 @@ pmu: common/pmu/pg/pg_sw_gp10b.h, common/pmu/pg/pg_sw_gv11b.c, common/pmu/pg/pg_sw_gv11b.h, + common/pmu/pg/pg_sw_ga10b.c, + common/pmu/pg/pg_sw_ga10b.h, common/pmu/pg/pmu_aelpg.c, common/pmu/pg/pmu_pg.c, common/pmu/pg/pmu_pg.h, diff --git a/arch/nvgpu-gpu_hw.yaml b/arch/nvgpu-gpu_hw.yaml index 7871451d0..3f26fc045 100644 --- a/arch/nvgpu-gpu_hw.yaml +++ b/arch/nvgpu-gpu_hw.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved. +# Copyright (c) 2019-2021, NVIDIA CORPORATION. All Rights Reserved. # # Define meta elements and units for describing GPU HW interactions in # nvgpu. @@ -221,4 +221,73 @@ headers: include/nvgpu/hw/tu104/hw_trim_tu104.h, include/nvgpu/hw/tu104/hw_usermode_tu104.h, include/nvgpu/hw/tu104/hw_xp_tu104.h, - include/nvgpu/hw/tu104/hw_xve_tu104.h ] + include/nvgpu/hw/tu104/hw_xve_tu104.h, + include/nvgpu/hw/ga100/hw_bus_ga100.h, + include/nvgpu/hw/ga100/hw_ce_ga100.h, + include/nvgpu/hw/ga100/hw_ctrl_ga100.h, + include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h, + include/nvgpu/hw/ga100/hw_falcon_ga100.h, + include/nvgpu/hw/ga100/hw_fb_ga100.h, + include/nvgpu/hw/ga100/hw_flush_ga100.h, + include/nvgpu/hw/ga100/hw_func_ga100.h, + include/nvgpu/hw/ga100/hw_fuse_ga100.h, + include/nvgpu/hw/ga100/hw_gc6_ga100.h, + include/nvgpu/hw/ga100/hw_gmmu_ga100.h, + include/nvgpu/hw/ga100/hw_gr_ga100.h, + include/nvgpu/hw/ga100/hw_ltc_ga100.h, + include/nvgpu/hw/ga100/hw_mc_ga100.h, + include/nvgpu/hw/ga100/hw_pbdma_ga100.h, + include/nvgpu/hw/ga100/hw_perf_ga100.h, + include/nvgpu/hw/ga100/hw_pgsp_ga100.h, + include/nvgpu/hw/ga100/hw_pram_ga100.h, + include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h, + include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h, + include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h, + include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h, + include/nvgpu/hw/ga100/hw_pri_sys_ga100.h, + include/nvgpu/hw/ga100/hw_proj_ga100.h, + include/nvgpu/hw/ga100/hw_psec_ga100.h, + include/nvgpu/hw/ga100/hw_pwr_ga100.h, + include/nvgpu/hw/ga100/hw_ram_ga100.h, + include/nvgpu/hw/ga100/hw_runlist_ga100.h, + include/nvgpu/hw/ga100/hw_smcarb_ga100.h, + include/nvgpu/hw/ga100/hw_timer_ga100.h, + include/nvgpu/hw/ga100/hw_top_ga100.h, + include/nvgpu/hw/ga100/hw_pnvdec_ga100.h, + include/nvgpu/hw/ga100/hw_therm_ga100.h, + include/nvgpu/hw/ga100/hw_trim_ga100.h, + include/nvgpu/hw/ga100/hw_xp_ga100.h, + include/nvgpu/hw/ga100/hw_xve_ga100.h, + include/nvgpu/hw/ga100/hw_fbpa_ga100.h, + include/nvgpu/hw/ga10b/hw_bus_ga10b.h, + include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h, + include/nvgpu/hw/ga10b/hw_ce_ga10b.h, + include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h, + include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h, + include/nvgpu/hw/ga10b/hw_falcon_ga10b.h, + include/nvgpu/hw/ga10b/hw_fb_ga10b.h, + include/nvgpu/hw/ga10b/hw_flush_ga10b.h, + include/nvgpu/hw/ga10b/hw_func_ga10b.h, + include/nvgpu/hw/ga10b/hw_fuse_ga10b.h, + include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h, + include/nvgpu/hw/ga10b/hw_gr_ga10b.h, + include/nvgpu/hw/ga10b/hw_ltc_ga10b.h, + include/nvgpu/hw/ga10b/hw_mc_ga10b.h, + include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h, + include/nvgpu/hw/ga10b/hw_perf_ga10b.h, + include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h, + include/nvgpu/hw/ga10b/hw_pram_ga10b.h, + include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h, + include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h, + include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h, + include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h, + include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h, + include/nvgpu/hw/ga10b/hw_proj_ga10b.h, + include/nvgpu/hw/ga10b/hw_priscv_ga10b.h, + include/nvgpu/hw/ga10b/hw_pwr_ga10b.h, + include/nvgpu/hw/ga10b/hw_ram_ga10b.h, + include/nvgpu/hw/ga10b/hw_runlist_ga10b.h, + include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h, + include/nvgpu/hw/ga10b/hw_therm_ga10b.h, + include/nvgpu/hw/ga10b/hw_timer_ga10b.h, + include/nvgpu/hw/ga10b/hw_top_ga10b.h ] diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index 979451eec..c9b660df5 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -18,7 +18,11 @@ bus: owner: Terje B sources: [ hal/bus/bus_gk20a.c, hal/bus/bus_gv100.c, hal/bus/bus_gv100.h, - hal/bus/bus_tu104.c, hal/bus/bus_tu104.h ] + hal/bus/bus_tu104.c, hal/bus/bus_tu104.h, + hal/bus/bus_ga10b.c, + hal/bus/bus_ga10b.h, + hal/bus/bus_ga100.c, + hal/bus/bus_ga100.h ] ltc: owner: Seshendra G @@ -30,14 +34,19 @@ ltc: hal/ltc/ltc_gp10b_fusa.c, hal/ltc/ltc_gp10b.h, hal/ltc/ltc_gv11b_fusa.c, - hal/ltc/ltc_gv11b.h ] + hal/ltc/ltc_gv11b.h, + hal/ltc/ltc_ga10b.h, + hal/ltc/ltc_ga10b_fusa.c ] + ltc: safe: no sources: [ hal/ltc/ltc_gm20b.c, hal/ltc/ltc_gm20b_dbg.c, hal/ltc/ltc_gp10b.c, hal/ltc/ltc_tu104.c, - hal/ltc/ltc_tu104.h ] + hal/ltc/ltc_tu104.h, + hal/ltc/ltc_ga10b.c ] + intr_fusa: safe: yes sources: [ hal/ltc/intr/ltc_intr_gp10b_fusa.c, @@ -48,7 +57,9 @@ ltc: safe: no sources: [ hal/ltc/intr/ltc_intr_gm20b.c, hal/ltc/intr/ltc_intr_gm20b.h, - hal/ltc/intr/ltc_intr_gp10b.c ] + hal/ltc/intr/ltc_intr_gp10b.c, + hal/ltc/intr/ltc_intr_ga10b.h, + hal/ltc/intr/ltc_intr_ga10b_fusa.c ] init_fusa: safe: yes @@ -68,6 +79,14 @@ init: hal/init/hal_gp10b.h, hal/init/hal_tu104.c, hal/init/hal_tu104.h, + hal/init/hal_ga100.c, + hal/init/hal_ga100.h, + hal/init/hal_ga10b.c, + hal/init/hal_ga10b.h, + hal/init/hal_ga100_litter.c, + hal/init/hal_ga100_litter.h, + hal/init/hal_ga10b_litter.c, + hal/init/hal_ga10b_litter.h, hal/init/hal_gm20b_litter.c, hal/init/hal_gm20b_litter.h, hal/init/hal_gp10b_litter.c, @@ -82,7 +101,11 @@ priv_ring_fusa: hal/priv_ring/priv_ring_gm20b_fusa.c, hal/priv_ring/priv_ring_gm20b.h, hal/priv_ring/priv_ring_gp10b_fusa.c, - hal/priv_ring/priv_ring_gp10b.h ] + hal/priv_ring/priv_ring_gp10b.h, + hal/priv_ring/priv_ring_ga10b_fusa.c, + hal/priv_ring/priv_ring_ga10b.h, + hal/priv_ring/priv_ring_ga100_fusa.c, + hal/priv_ring/priv_ring_ga100.h ] priv_ring: safe: no @@ -95,7 +118,9 @@ ptimer_fusa: safe: yes owner: Terje B sources: [ hal/ptimer/ptimer_gk20a_fusa.c, - hal/ptimer/ptimer_gk20a.h ] + hal/ptimer/ptimer_gk20a.h, + hal/ptimer/ptimer_ga10b_fusa.c, + hal/ptimer/ptimer_ga10b.h ] ptimer: safe: no @@ -120,7 +145,11 @@ cg: hal/power_features/cg/gp10b_gating_reglist.c, hal/power_features/cg/gp10b_gating_reglist.h, hal/power_features/cg/tu104_gating_reglist.c, - hal/power_features/cg/tu104_gating_reglist.h ] + hal/power_features/cg/tu104_gating_reglist.h, + hal/power_features/cg/ga10b_gating_reglist.c, + hal/power_features/cg/ga10b_gating_reglist.h, + hal/power_features/cg/ga100_gating_reglist.c, + hal/power_features/cg/ga100_gating_reglist.h ] rc: safe: no @@ -141,7 +170,9 @@ clk: owner: Ramesh M gpu: dgpu sources: [ hal/clk/clk_tu104.c, - hal/clk/clk_tu104.h ] + hal/clk/clk_tu104.h, + hal/clk/clk_ga100.c, + hal/clk/clk_ga100.h ] clk_mon: safe: yes @@ -168,14 +199,19 @@ fifo: sources: [ hal/fifo/userd_gk20a.c, hal/fifo/userd_gk20a.h, hal/fifo/userd_gv11b.c, - hal/fifo/userd_gv11b.h ] + hal/fifo/userd_gv11b.h, + hal/fifo/userd_ga10b.c, + hal/fifo/userd_ga10b.h ] + ramfc_fusa: safe: yes sources: [ hal/fifo/ramin_gk20a_fusa.c, hal/fifo/ramfc_gp10b_fusa.c, hal/fifo/ramfc_gp10b.h, hal/fifo/ramfc_gv11b_fusa.c, - hal/fifo/ramfc_gv11b.h ] + hal/fifo/ramfc_gv11b.h, + hal/fifo/ramfc_ga10b_fusa.c, + hal/fifo/ramfc_ga10b.h ] ramfc: safe: no @@ -190,7 +226,9 @@ fifo: sources: [ hal/fifo/ramin_gv11b.h, hal/fifo/ramin_gm20b.h, hal/fifo/ramin_gv11b_fusa.c, - hal/fifo/ramin_gm20b_fusa.c ] + hal/fifo/ramin_gm20b_fusa.c, + hal/fifo/ramin_ga10b_fusa.c, + hal/fifo/ramin_ga10b.h ] ramin: safe: no @@ -210,7 +248,12 @@ fifo: hal/fifo/runlist_fifo_gv11b_fusa.c, hal/fifo/runlist_fifo_gv11b.h, hal/fifo/runlist_ram_gv11b_fusa.c, - hal/fifo/runlist_ram_gv11b.h ] + hal/fifo/runlist_ram_gv11b.h, + hal/fifo/runlist_fifo_ga10b.h, + hal/fifo/runlist_fifo_ga10b.c, + hal/fifo/runlist_fifo_ga10b_fusa.c, + hal/fifo/runlist_fifo_ga100.h, + hal/fifo/runlist_fifo_ga100_fusa.c ] runlist: safe: no @@ -221,7 +264,9 @@ fifo: hal/fifo/runlist_ram_gk20a.c, hal/fifo/runlist_ram_gk20a.h, hal/fifo/runlist_ram_tu104.c, - hal/fifo/runlist_ram_tu104.h ] + hal/fifo/runlist_ram_tu104.h, + hal/fifo/runlist_ga10b.h, + hal/fifo/runlist_ga10b_fusa.c ] channel_fusa: safe: yes @@ -230,7 +275,12 @@ fifo: hal/fifo/channel_gm20b_fusa.c, hal/fifo/channel_gm20b.h, hal/fifo/channel_gv11b_fusa.c, - hal/fifo/channel_gv11b.h ] + hal/fifo/channel_gv11b.h, + hal/fifo/channel_ga10b_fusa.c, + hal/fifo/channel_ga10b.h, + hal/fifo/channel_ga100_fusa.c, + hal/fifo/channel_ga100.h ] + channel: safe: no sources: [ hal/fifo/channel_gk20a.c, @@ -246,7 +296,9 @@ fifo: tsg: safe: no - sources: [ hal/fifo/tsg_gk20a.c ] + sources: [ hal/fifo/tsg_gk20a.c, + hal/fifo/tsg_ga10b.h, + hal/fifo/tsg_ga10b.c ] fifo_fusa: safe: yes @@ -259,7 +311,14 @@ fifo: hal/fifo/fifo_gk20a_fusa.c, hal/fifo/fifo_gk20a.h, hal/fifo/fifo_gv11b_fusa.c, - hal/fifo/fifo_gv11b.h ] + hal/fifo/fifo_gv11b.h, + hal/fifo/fifo_ga10b_fusa.c, + hal/fifo/fifo_intr_ga10b_fusa.c, + hal/fifo/ctxsw_timeout_ga10b_fusa.c, + hal/fifo/ctxsw_timeout_ga10b.h, + hal/fifo/fifo_intr_ga10b.h, + hal/fifo/fifo_ga10b.h ] + fifo: safe: no sources: [ hal/fifo/fifo_intr_gk20a.c, @@ -282,7 +341,10 @@ fifo: sources: [ hal/fifo/engine_status_gm20b_fusa.c, hal/fifo/engine_status_gm20b.h, hal/fifo/engine_status_gv100_fusa.c, - hal/fifo/engine_status_gv100.h ] + hal/fifo/engine_status_gv100.h, + hal/fifo/engine_status_ga10b_fusa.c, + hal/fifo/engine_status_ga10b.h ] + engine_status: safe: no sources: [ hal/fifo/engine_status_gm20b.c ] @@ -299,10 +361,19 @@ fifo: sources: [ hal/fifo/engines_gm20b.c, hal/fifo/engines_gm20b.h ] + pbdma_status_fusa: + safe: no + sources: [ hal/fifo/pbdma_status_ga10b_fusa.c, + hal/fifo/pbdma_status_ga10b.h ] + pbdma_status: safe: yes sources: [ hal/fifo/pbdma_status_gm20b_fusa.c, - hal/fifo/pbdma_status_gm20b.h ] + hal/fifo/pbdma_status_gm20b.h, + hal/fifo/pbdma_ga10b_fusa.c, + hal/fifo/pbdma_ga10b.h, + hal/fifo/pbdma_ga100_fusa.c, + hal/fifo/pbdma_ga100.h ] pbdma_fusa: safe: yes @@ -318,12 +389,15 @@ fifo: sources: [ hal/fifo/pbdma_gm20b.c, hal/fifo/pbdma_gp10b.c, hal/fifo/pbdma_tu104.c, - hal/fifo/pbdma_tu104.h ] + hal/fifo/pbdma_tu104.h, + hal/fifo/pbdma_ga10b.c ] preempt_fusa: safe: yes sources: [ hal/fifo/preempt_gv11b_fusa.c, - hal/fifo/preempt_gv11b.h ] + hal/fifo/preempt_gv11b.h, + hal/fifo/preempt_ga10b_fusa.c, + hal/fifo/preempt_ga10b.h ] preempt: safe: no @@ -333,13 +407,21 @@ fifo: usermode_fusa: safe: yes sources: [ hal/fifo/usermode_gv11b_fusa.c, - hal/fifo/usermode_gv11b.h ] + hal/fifo/usermode_gv11b.h, + hal/fifo/usermode_ga10b_fusa.c, + hal/fifo/usermode_ga10b.h ] usermode: safe: no sources: [ hal/fifo/usermode_tu104.c, hal/fifo/usermode_tu104.h ] + utils_fusa: + safe: no + sources: [ hal/fifo/fifo_utils_ga10b_fusa.c, + hal/fifo/fifo_utils_ga10b.h ] + + fuse_fusa: safe: yes owner: Seema K @@ -355,12 +437,18 @@ fuse: hal/fuse/fuse_gp106.c, hal/fuse/fuse_gp106.h, hal/fuse/fuse_tu104.c, - hal/fuse/fuse_tu104.h ] + hal/fuse/fuse_tu104.h, + hal/fuse/fuse_ga10b.h, + hal/fuse/fuse_ga100.h, + hal/fuse/fuse_ga10b.c, + hal/fuse/fuse_ga100.c ] gsp: safe: no sources: [ hal/gsp/gsp_tu104.c, - hal/gsp/gsp_tu104.h ] + hal/gsp/gsp_tu104.h, + hal/gsp/gsp_ga10b.h, + hal/gsp/gsp_ga10b.c ] mm: safe: yes @@ -375,7 +463,10 @@ mm: hal/mm/gmmu/gmmu_gp10b_fusa.c, hal/mm/gmmu/gmmu_gp10b.h, hal/mm/gmmu/gmmu_gv11b_fusa.c, - hal/mm/gmmu/gmmu_gv11b.h ] + hal/mm/gmmu/gmmu_gv11b.h, + hal/mm/gmmu/gmmu_ga10b_fusa.c, + hal/mm/gmmu/gmmu_ga10b.h ] + gmmu: safe: no sources: [ hal/mm/gmmu/gmmu_gk20a.c, @@ -389,10 +480,14 @@ mm: cache: safe: no sources: [ hal/mm/cache/flush_gk20a.c ] + mmu_fault: safe: yes sources: [ hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c, - hal/mm/mmu_fault/mmu_fault_gv11b.h ] + hal/mm/mmu_fault/mmu_fault_gv11b.h, + hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c, + hal/mm/mmu_fault/mmu_fault_ga10b.h ] + mm_fusa: safe: yes sources: [ hal/mm/mm_gp10b_fusa.c, @@ -435,7 +530,9 @@ therm_fusa: safe: yes owner: Seshendra G sources: [ hal/therm/therm_gv11b_fusa.c, - hal/therm/therm_gv11b.h ] + hal/therm/therm_gv11b.h, + hal/therm/therm_ga10b_fusa.c, + hal/therm/therm_ga10b.h ] therm: safe: no @@ -457,7 +554,11 @@ cbc: hal/cbc/cbc_gv11b.c, hal/cbc/cbc_gv11b.h, hal/cbc/cbc_tu104.c, - hal/cbc/cbc_tu104.h ] + hal/cbc/cbc_tu104.h, + hal/cbc/cbc_ga10b.c, + hal/cbc/cbc_ga10b.h, + hal/cbc/cbc_ga100.c, + hal/cbc/cbc_ga100.h ] ce_fusa: safe: yes @@ -465,7 +566,9 @@ ce_fusa: sources: [ hal/ce/ce_gp10b_fusa.c, hal/ce/ce_gp10b.h, hal/ce/ce_gv11b_fusa.c, - hal/ce/ce_gv11b.h ] + hal/ce/ce_gv11b.h, + hal/ce/ce_ga10b_fusa.c, + hal/ce/ce_ga10b.h ] ce: safe: no @@ -482,12 +585,17 @@ gr: ecc_fusa: safe: yes sources: [hal/gr/ecc/ecc_gv11b_fusa.c, - hal/gr/ecc/ecc_gv11b.h ] + hal/gr/ecc/ecc_gv11b.h, + hal/gr/ecc/ecc_ga10b_fusa.c, + hal/gr/ecc/ecc_ga10b.h ] + ecc: safe: no sources: [hal/gr/ecc/ecc_gv11b.c, hal/gr/ecc/ecc_gp10b.c, - hal/gr/ecc/ecc_gp10b.h ] + hal/gr/ecc/ecc_gp10b.h, + hal/gr/ecc/ecc_ga10b.c ] + ctxsw_prog_fusa: safe: yes sources: [ hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c, @@ -495,13 +603,23 @@ gr: hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c, hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h, hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c, - hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h ] + hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h, + hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c, + hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h, + hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c, + hal/gr/ctxsw_prog/ctxsw_prog_ga100.h] + ctxsw_prog: safe: no sources: [ hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c, hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c, hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c, - hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c] + hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c, + hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c, + hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c, + hal/gr/ctxsw_prog/ctxsw_prog_ga100.c, + hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c ] + config_fusa: safe: yes sources: [ hal/gr/config/gr_config_gm20b_fusa.c, @@ -520,7 +638,12 @@ gr: hal/gr/init/gr_init_gp10b_fusa.c, hal/gr/init/gr_init_gp10b.h, hal/gr/init/gr_init_gv11b_fusa.c, - hal/gr/init/gr_init_gv11b.h ] + hal/gr/init/gr_init_gv11b.h, + hal/gr/init/gr_init_ga10b_fusa.c, + hal/gr/init/gr_init_ga100_fusa.c, + hal/gr/init/gr_init_ga100.h, + hal/gr/init/gr_init_ga10b.h ] + init: safe: no sources: [ hal/gr/init/gr_init_gm20b.c, @@ -529,7 +652,12 @@ gr: hal/gr/init/gr_init_gv100.h, hal/gr/init/gr_init_gv11b.c, hal/gr/init/gr_init_tu104.c, - hal/gr/init/gr_init_tu104.h ] + hal/gr/init/gr_init_tu104.h, + hal/gr/init/gr_init_ga10b.c, + hal/gr/init/gr_init_ga10b.h, + hal/gr/init/gr_init_ga100.c, + hal/gr/init/gr_init_ga100.h ] + intr_fusa: safe: yes sources: [ hal/gr/intr/gr_intr_gm20b_fusa.c, @@ -537,7 +665,12 @@ gr: hal/gr/intr/gr_intr_gp10b_fusa.c, hal/gr/intr/gr_intr_gp10b.h, hal/gr/intr/gr_intr_gv11b_fusa.c, - hal/gr/intr/gr_intr_gv11b.h ] + hal/gr/intr/gr_intr_gv11b.h, + hal/gr/intr/gr_intr_ga10b_fusa.c, + hal/gr/intr/gr_intr_ga10b.h, + hal/gr/intr/gr_intr_ga100_fusa.c, + hal/gr/intr/gr_intr_ga100.h ] + intr: safe: no sources: [ hal/gr/intr/gr_intr_gm20b.c, @@ -551,12 +684,19 @@ gr: hal/gr/falcon/gr_falcon_gp10b_fusa.c, hal/gr/falcon/gr_falcon_gp10b.h, hal/gr/falcon/gr_falcon_gv11b_fusa.c, - hal/gr/falcon/gr_falcon_gv11b.h ] + hal/gr/falcon/gr_falcon_gv11b.h, + hal/gr/falcon/gr_falcon_ga10b_fusa.c, + hal/gr/falcon/gr_falcon_ga10b.h ] + falcon: safe: no sources: [ hal/gr/falcon/gr_falcon_gm20b.c, hal/gr/falcon/gr_falcon_tu104.c, - hal/gr/falcon/gr_falcon_tu104.h ] + hal/gr/falcon/gr_falcon_tu104.h, + hal/gr/falcon/gr_falcon_ga10b.c, + hal/gr/falcon/gr_falcon_ga100.c, + hal/gr/falcon/gr_falcon_ga100.h ] + fecs_trace: safe: no sources: [ hal/gr/fecs_trace/fecs_trace_gm20b.c, @@ -575,7 +715,10 @@ gr: hal/gr/zbc/zbc_gp10b.c, hal/gr/zbc/zbc_gp10b.h, hal/gr/zbc/zbc_gv11b.c, - hal/gr/zbc/zbc_gv11b.h ] + hal/gr/zbc/zbc_gv11b.h, + hal/gr/zbc/zbc_ga10b.c, + hal/gr/zbc/zbc_ga10b.h ] + zcull: safe: no sources: [ hal/gr/zcull/zcull_gm20b.c, @@ -592,7 +735,13 @@ gr: hal/gr/gr/gr_tu104.c, hal/gr/gr/gr_tu104.h, include/nvgpu/gr/warpstate.h, hal/gr/gr/gr_pri_gk20a.h, - hal/gr/gr/gr_pri_gv11b.h ] + hal/gr/gr/gr_pri_gv11b.h, + hal/gr/gr/gr_ga10b.c, + hal/gr/gr/gr_ga10b.h, + hal/gr/gr/gr_ga100.c, + hal/gr/gr/gr_ga100.h, + hal/gr/gr/gr_pri_ga10b.h ] + regops: safe: no @@ -608,13 +757,23 @@ regops: hal/regops/allowlist_gv11b.c, hal/regops/allowlist_gv11b.h, hal/regops/allowlist_tu104.c, - hal/regops/allowlist_tu104.h ] + hal/regops/allowlist_tu104.h, + hal/regops/regops_ga10b.c, + hal/regops/regops_ga100.c, + hal/regops/regops_ga10b.h, + hal/regops/regops_ga100.h, + hal/regops/allowlist_ga10b.c, + hal/regops/allowlist_ga10b.h, + hal/regops/allowlist_ga100.c, + hal/regops/allowlist_ga100.h ] falcon_fusa: safe: yes owner: Sagar K sources: [ hal/falcon/falcon_gk20a_fusa.c, - hal/falcon/falcon_gk20a.h ] + hal/falcon/falcon_gk20a.h, + hal/falcon/falcon_ga10b_fusa.c, + hal/falcon/falcon_ga10b.h ] falcon: safe: no @@ -629,7 +788,11 @@ mc_fusa: hal/mc/mc_gp10b_fusa.c, hal/mc/mc_gp10b.h, hal/mc/mc_gv11b_fusa.c, - hal/mc/mc_gv11b.h ] + hal/mc/mc_gv11b.h, + hal/mc/mc_intr_ga10b_fusa.c, + hal/mc/mc_intr_ga10b.h, + hal/mc/mc_ga10b_fusa.c, + hal/mc/mc_ga10b.h ] mc: safe: no @@ -651,7 +814,17 @@ fb_fusa: hal/fb/ecc/fb_ecc_gv11b.h, hal/fb/ecc/fb_ecc_gv11b_fusa.c, hal/fb/intr/fb_intr_gv11b.h, hal/fb/intr/fb_intr_gv11b_fusa.c, hal/fb/fb_mmu_fault_gv11b.h, hal/fb/fb_mmu_fault_gv11b_fusa.c, - hal/fb/intr/fb_intr_ecc_gv11b.h, hal/fb/intr/fb_intr_ecc_gv11b_fusa.c ] + hal/fb/intr/fb_intr_ecc_gv11b.h, hal/fb/intr/fb_intr_ecc_gv11b_fusa.c, + hal/fb/fb_ga10b.h, + hal/fb/fb_ga10b_fusa.c, + hal/fb/ecc/fb_ecc_ga10b.h, + hal/fb/ecc/fb_ecc_ga10b_fusa.c, + hal/fb/intr/fb_intr_ga10b.h, + hal/fb/intr/fb_intr_ga10b_fusa.c, + hal/fb/fb_mmu_fault_ga10b.h, + hal/fb/fb_mmu_fault_ga10b_fusa.c, + hal/fb/intr/fb_intr_ecc_ga10b.h, + hal/fb/intr/fb_intr_ecc_ga10b_fusa.c ] fb: safe: no @@ -665,7 +838,12 @@ fb: hal/fb/intr/fb_intr_gv100.h, hal/fb/intr/fb_intr_gv100.c, hal/fb/fb_mmu_fault_tu104.h, hal/fb/fb_mmu_fault_tu104.c, hal/fb/intr/fb_intr_tu104.c, hal/fb/intr/fb_intr_tu104.h, - hal/fb/intr/fb_intr_ecc_gv11b.c ] + hal/fb/intr/fb_intr_ecc_gv11b.c, + hal/fb/fb_ga10b.c, + hal/fb/fb_ga100.h, + hal/fb/fb_ga100.c, + hal/fb/vab/vab_ga10b.c, + hal/fb/vab/vab_ga10b.h ] pmu_fusa: safe: yes @@ -685,7 +863,11 @@ pmu: hal/pmu/pmu_gp10b.h, hal/pmu/pmu_gv11b.c, hal/pmu/pmu_tu104.c, - hal/pmu/pmu_tu104.h ] + hal/pmu/pmu_tu104.h, + hal/pmu/pmu_ga10b.h, + hal/pmu/pmu_ga10b.c, + hal/pmu/pmu_ga100.h, + hal/pmu/pmu_ga100.c ] nvlink: safe: yes @@ -718,7 +900,9 @@ netlist_fusa: gpu: both sources: [ include/nvgpu/gops/netlist.h, hal/netlist/netlist_gv11b_fusa.c, - hal/netlist/netlist_gv11b.h ] + hal/netlist/netlist_gv11b.h, + hal/netlist/netlist_ga10b_fusa.c, + hal/netlist/netlist_ga10b.h ] netlist: safe: no @@ -731,14 +915,18 @@ netlist: hal/netlist/netlist_gv100.c, hal/netlist/netlist_gv100.h, hal/netlist/netlist_tu104.c, - hal/netlist/netlist_tu104.h ] + hal/netlist/netlist_tu104.h, + hal/netlist/netlist_ga100.c, + hal/netlist/netlist_ga100.h ] nvdec: safe: no sources: [ hal/nvdec/nvdec_gp106.c, hal/nvdec/nvdec_gp106.h, hal/nvdec/nvdec_tu104.c, - hal/nvdec/nvdec_tu104.h ] + hal/nvdec/nvdec_tu104.h, + hal/nvdec/nvdec_ga100.c, + hal/nvdec/nvdec_ga100.h ] perf: safe: no @@ -748,7 +936,11 @@ perf: hal/perf/perf_gv11b.c, hal/perf/perf_gv11b.h, hal/perf/perf_tu104.c, - hal/perf/perf_tu104.h ] + hal/perf/perf_tu104.h, + hal/perf/perf_ga10b.c, + hal/perf/perf_ga10b.h, + hal/perf/perf_ga100.c, + hal/perf/perf_ga100.h ] pramin: safe: yes @@ -776,14 +968,21 @@ class: sources: [ hal/class/class_gm20b.c, hal/class/class_gp10b.c, hal/class/class_tu104.c, - hal/class/class_tu104.h ] + hal/class/class_tu104.h, + hal/class/class_ga10b.h, + hal/class/class_ga10b.c, + hal/class/class_ga100.h, + hal/class/class_ga100.c ] + func: safe: yes owner: Terje B gpu: dgpu sources: [ hal/func/func_tu104.c, - hal/func/func_tu104.h ] + hal/func/func_tu104.h, + hal/func/func_ga10b.c, + hal/func/func_ga10b.h ] top_fusa: safe: yes @@ -803,7 +1002,9 @@ top: hal/top/top_gp106.h, hal/top/top_gp10b.c, hal/top/top_gv100.c, - hal/top/top_gv100.h ] + hal/top/top_gv100.h, + hal/top/top_ga10b.h, + hal/top/top_ga10b_fusa.c ] bios: safe: yes @@ -834,3 +1035,17 @@ cic: sources: [ hal/cic/cic_gv11b_fusa.c, hal/cic/cic_lut_gv11b_fusa.c, hal/cic/cic_gv11b.h ] + +misc: + safe: no + owner: Vedashree V + sources: [ nvgpu_next_gpuid.h ] + +grmgr: + safe: no + owner: Lakshmanan M + sources: [ hal/grmgr/grmgr_ga10b.c, + hal/grmgr/grmgr_ga10b.h, + hal/grmgr/grmgr_ga100.c, + hal/grmgr/grmgr_ga100.h,] + diff --git a/arch/nvgpu-hal-vgpu.yaml b/arch/nvgpu-hal-vgpu.yaml index 67577c733..09e4a0f85 100644 --- a/arch/nvgpu-hal-vgpu.yaml +++ b/arch/nvgpu-hal-vgpu.yaml @@ -9,7 +9,9 @@ init: sources: [ hal/vgpu/init/init_hal_vgpu.c, hal/vgpu/init/init_hal_vgpu.h, hal/vgpu/init/vgpu_hal_gv11b.c, - hal/vgpu/init/vgpu_hal_gv11b.h ] + hal/vgpu/init/vgpu_hal_gv11b.h, + hal/vgpu/init/vgpu_hal_ga10b.c, + hal/vgpu/init/vgpu_hal_ga10b.h ] fifo: safe : no diff --git a/arch/nvgpu-linux.yaml b/arch/nvgpu-linux.yaml index 8beff0201..74598f9f1 100644 --- a/arch/nvgpu-linux.yaml +++ b/arch/nvgpu-linux.yaml @@ -183,7 +183,9 @@ platform: os/linux/platform_gk20a_tegra.h, os/linux/platform_gp10b.h, os/linux/platform_gp10b_tegra.c, - os/linux/platform_gv11b_tegra.c ] + os/linux/platform_gv11b_tegra.c, + os/linux/platform_ga10b_tegra.c, + os/linux/nvlink/hal/ga10b_mssnvlink.c ] rwsem: sources: [ os/linux/rwsem.c ] @@ -216,6 +218,7 @@ vgpu: sources: [ os/linux/vgpu/fecs_trace_vgpu_linux.c, os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c, os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.h, + os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c, os/linux/vgpu/platform_vgpu_tegra.c, os/linux/vgpu/platform_vgpu_tegra.h, os/linux/vgpu/sysfs_vgpu.c, diff --git a/arch/nvgpu-next-common.yaml b/arch/nvgpu-next-common.yaml deleted file mode 100644 index f02600c80..000000000 --- a/arch/nvgpu-next-common.yaml +++ /dev/null @@ -1,180 +0,0 @@ -# -# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# - -# Common elements and units in nvgpu. -# - -## -## Common elements. -## - -nvgpu_next_fifo: - safe: no - owner: Seshendra G - children: - engines: - safe: no - sources: [ include/nvgpu/nvgpu_next_engines.h, - common/fifo/nvgpu_next_engines.c ] - - runlist: - safe: no - sources: [ include/nvgpu/nvgpu_next_runlist.h, - common/fifo/nvgpu_next_runlist.c ] - - pbdma: - safe: no - sources: [ include/nvgpu/nvgpu_next_pbdma.h ] - - fifo: - safe: no - sources: [ include/nvgpu/nvgpu_next_gops_fifo.h ] - -nvgpu_next_sim: - safe: no - owner: Vedashree V - sources: [ include/nvgpu/nvgpu_next_sim.h, - common/sim/nvgpu_next_sim_netlist.c, - common/sim/nvgpu_next_sim.c ] - -nvgpu_next_netlist: - safe: no - owner: Vedashree V - sources: [ include/nvgpu/nvgpu_next_gops_fifo.h, - include/nvgpu/nvgpu_next_netlist.h, - common/netlist/nvgpu_next_netlist_priv.h, - common/netlist/nvgpu_next_netlist.c ] - -nvgpu_next_gr: - safe: no - owner: Vedashree V - sources: [ include/nvgpu/nvgpu_next_gops_gr.h, - include/nvgpu/gr/nvgpu_next_gr.h, - include/nvgpu/gr/nvgpu_next_fs_state.h, - include/nvgpu/gr/nvgpu_next_gr_ecc.h, - include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h, - common/gr/nvgpu_next_fs_state.c, - common/gr/nvgpu_next_gr.c ] - -nvgpu_next_bios: - safe: no - owner: Thomas F - sources: [ common/vbios/bios_sw_ga100.c, - common/vbios/bios_sw_ga100.h ] - -nvgpu_next_device: - safe: yes - owner: Alex W - sources: [ include/nvgpu/nvgpu_next_device.h ] - -nvgpu_next_ltc: - safe: no - owner: Antony - sources: [ include/nvgpu/nvgpu_next_gops_ltc.h, - include/nvgpu/nvgpu_next_gops_ltc_intr.h ] - -nvgpu_next_ce: - safe: no - owner: Antony - sources: [ include/nvgpu/nvgpu_next_gops_ce.h ] - -nvgpu_next_grmgr: - safe: no - owner: Lakshmanan M - sources: [ include/nvgpu/nvgpu_next_gops_grmgr.h ] - -nvgpu_next_priv_ring: - safe: no - owner: Lakshmanan M - sources: [ include/nvgpu/nvgpu_next_gops_priv_ring.h ] - -nvgpu_next_pmu_perfmon: - safe: no - owner: Ramesh M - sources: [ common/pmu/perfmon/pmu_perfmon_sw_ga10b.c, - common/pmu/perfmon/pmu_perfmon_sw_ga10b.h ] - -nvgpu_next_mc: - safe: yes - owner: Antony Clince Alex - sources: [ common/mc/nvgpu_next_mc.c, - include/nvgpu/nvgpu_next_mc.h ] - -nvgpu_next_cic: - safe: yes - owner: Tejal Kudav - sources: [ include/nvgpu/nvgpu_next_cic.h, - common/cic/nvgpu_next_cic.c ] - -nvgpu_next_pmu_pg: - safe: no - owner: Ramesh M - sources: [ common/pmu/pg/pg_sw_ga10b.c, - common/pmu/pg/pg_sw_ga10b.h ] - -nvgpu_next_err: - safe: yes - owner: Antony Clince Alex - sources: [ include/nvgpu/nvgpu_next_err.h ] - -nvgpu_next_acr_fusa: - safe: no - owner: Deepak G - sources: [ common/acr/nvgpu_next_acr_bootstrap.c, - common/acr/nvgpu_next_acr_bootstrap.h, - include/nvgpu/riscv.h, - common/riscv/riscv.c ] - -nvgpu_next_acr: - safe: no - owner: Deepak G - sources: [ common/acr/acr_sw_ga10b.c, - common/acr/acr_sw_ga10b.h, - common/acr/acr_sw_ga100.c, - common/acr/acr_sw_ga100.h ] - -nvgpu_next_falcon: - safe: no - owner: Deepak G - sources: [ common/falcon/falcon_sw_ga10b.c, - common/falcon/falcon_sw_ga10b.h ] - -nvgpu_next_litter: - safe: no - owner: Antony - sources: [ include/nvgpu/nvgpu_next_litter.h ] - -nvgpu_next_profiler: - safe: no - owner: Antony - sources: [ common/profiler/nvgpu_next_profiler.h, - common/profiler/nvgpu_next_profiler.c ] - -nvgpu_next_fb: - safe: no - owner: Vedashree V - sources: [ common/fb/nvgpu_next_fb.c ] - -nvgpu_next_utils: - safe: no - owner: Vedashree V - sources: [ include/nvgpu/nvgpu_next_errata.h ] diff --git a/arch/nvgpu-next-gpu_hw.yaml b/arch/nvgpu-next-gpu_hw.yaml deleted file mode 100644 index efd9ab3be..000000000 --- a/arch/nvgpu-next-gpu_hw.yaml +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# - -# Define meta elements and units for describing GPU HW interactions in -# nvgpu. -# - -nvgpu_next_headers: - safe: no - owner: Seshendra G - sources: [ include/nvgpu/hw/ga100/hw_bus_ga100.h, - include/nvgpu/hw/ga100/hw_ce_ga100.h, - include/nvgpu/hw/ga100/hw_ctrl_ga100.h, - include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h, - include/nvgpu/hw/ga100/hw_falcon_ga100.h, - include/nvgpu/hw/ga100/hw_fb_ga100.h, - include/nvgpu/hw/ga100/hw_flush_ga100.h, - include/nvgpu/hw/ga100/hw_func_ga100.h, - include/nvgpu/hw/ga100/hw_fuse_ga100.h, - include/nvgpu/hw/ga100/hw_gc6_ga100.h, - include/nvgpu/hw/ga100/hw_gmmu_ga100.h, - include/nvgpu/hw/ga100/hw_gr_ga100.h, - include/nvgpu/hw/ga100/hw_ltc_ga100.h, - include/nvgpu/hw/ga100/hw_mc_ga100.h, - include/nvgpu/hw/ga100/hw_pbdma_ga100.h, - include/nvgpu/hw/ga100/hw_perf_ga100.h, - include/nvgpu/hw/ga100/hw_pgsp_ga100.h, - include/nvgpu/hw/ga100/hw_pram_ga100.h, - include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h, - include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h, - include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h, - include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h, - include/nvgpu/hw/ga100/hw_pri_sys_ga100.h, - include/nvgpu/hw/ga100/hw_proj_ga100.h, - include/nvgpu/hw/ga100/hw_psec_ga100.h, - include/nvgpu/hw/ga100/hw_pwr_ga100.h, - include/nvgpu/hw/ga100/hw_ram_ga100.h, - include/nvgpu/hw/ga100/hw_runlist_ga100.h, - include/nvgpu/hw/ga100/hw_smcarb_ga100.h, - include/nvgpu/hw/ga100/hw_timer_ga100.h, - include/nvgpu/hw/ga100/hw_top_ga100.h, - include/nvgpu/hw/ga100/hw_pnvdec_ga100.h, - include/nvgpu/hw/ga100/hw_therm_ga100.h, - include/nvgpu/hw/ga100/hw_trim_ga100.h, - include/nvgpu/hw/ga100/hw_xp_ga100.h, - include/nvgpu/hw/ga100/hw_xve_ga100.h, - include/nvgpu/hw/ga100/hw_fbpa_ga100.h, - include/nvgpu/hw/ga10b/hw_bus_ga10b.h, - include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h, - include/nvgpu/hw/ga10b/hw_ce_ga10b.h, - include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h, - include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h, - include/nvgpu/hw/ga10b/hw_falcon_ga10b.h, - include/nvgpu/hw/ga10b/hw_fb_ga10b.h, - include/nvgpu/hw/ga10b/hw_flush_ga10b.h, - include/nvgpu/hw/ga10b/hw_func_ga10b.h, - include/nvgpu/hw/ga10b/hw_fuse_ga10b.h, - include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h, - include/nvgpu/hw/ga10b/hw_gr_ga10b.h, - include/nvgpu/hw/ga10b/hw_ltc_ga10b.h, - include/nvgpu/hw/ga10b/hw_mc_ga10b.h, - include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h, - include/nvgpu/hw/ga10b/hw_perf_ga10b.h, - include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h, - include/nvgpu/hw/ga10b/hw_pram_ga10b.h, - include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h, - include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h, - include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h, - include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h, - include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h, - include/nvgpu/hw/ga10b/hw_proj_ga10b.h, - include/nvgpu/hw/ga10b/hw_priscv_ga10b.h, - include/nvgpu/hw/ga10b/hw_pwr_ga10b.h, - include/nvgpu/hw/ga10b/hw_ram_ga10b.h, - include/nvgpu/hw/ga10b/hw_runlist_ga10b.h, - include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h, - include/nvgpu/hw/ga10b/hw_therm_ga10b.h, - include/nvgpu/hw/ga10b/hw_timer_ga10b.h, - include/nvgpu/hw/ga10b/hw_top_ga10b.h ] diff --git a/arch/nvgpu-next-hal-vgpu.yaml b/arch/nvgpu-next-hal-vgpu.yaml deleted file mode 100644 index 58e3eb327..000000000 --- a/arch/nvgpu-next-hal-vgpu.yaml +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# - -# VGPU HAL units. -# - -vgpu-next-init: - safe: no - owner: Aparna D - sources: [ hal/vgpu/init/vgpu_hal_ga10b.c, - hal/vgpu/init/vgpu_hal_ga10b.h ] diff --git a/arch/nvgpu-next-hal.yaml b/arch/nvgpu-next-hal.yaml deleted file mode 100644 index 20e8076f1..000000000 --- a/arch/nvgpu-next-hal.yaml +++ /dev/null @@ -1,427 +0,0 @@ -# -# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# - -# HAL units. These are the units that have access to HW. -# - -nvgpu_next_init: - safe: no - owner: Seshendra G - sources: [ hal/init/hal_ga100.c, - hal/init/hal_ga100.h, - hal/init/hal_ga10b.c, - hal/init/hal_ga10b.h, - hal/init/hal_ga100_litter.c, - hal/init/hal_ga100_litter.h, - hal/init/hal_ga10b_litter.c, - hal/init/hal_ga10b_litter.h ] - -nvgpu_next_class: - safe: no - owner: Seshendra G - sources: [ hal/class/class_ga10b.h, - hal/class/class_ga10b.c, - hal/class/class_ga100.h, - hal/class/class_ga100.c, - include/nvgpu/nvgpu_next_class.h ] - -nvgpu_next_top: - safe: no - owner: Seshendra G - sources: [ hal/top/top_ga10b.h, - hal/top/top_ga10b_fusa.c ] - -nvgpu_next_fuse: - safe: no - owner: Seshendra G - sources: [ include/nvgpu/nvgpu_next_gops_fuse.h, - include/nvgpu/nvgpu_next_fuse.h, - hal/fuse/fuse_ga10b.h, - hal/fuse/fuse_ga100.h, - hal/fuse/fuse_ga10b.c, - hal/fuse/fuse_ga100.c ] - -nvgpu_next_clk: - safe: no - sources: [ hal/clk/clk_ga100.c, - hal/clk/clk_ga100.h ] - -nvgpu_next_fifo: - safe: no - owner: Seshendra G - children: - runlist: - safe: no - sources: [ include/nvgpu/nvgpu_next_gops_runlist.h, - hal/fifo/runlist_ga10b.h, - hal/fifo/runlist_ga10b_fusa.c ] - - runlist_fusa: - safe: no - sources: [ hal/fifo/runlist_fifo_ga10b.h, - hal/fifo/runlist_fifo_ga10b.c, - hal/fifo/runlist_fifo_ga10b_fusa.c, - hal/fifo/runlist_fifo_ga100.h, - hal/fifo/runlist_fifo_ga100_fusa.c ] - - fifo_fusa: - safe: no - sources: [ hal/fifo/fifo_ga10b_fusa.c, - hal/fifo/fifo_intr_ga10b_fusa.c, - hal/fifo/ctxsw_timeout_ga10b_fusa.c, - hal/fifo/ctxsw_timeout_ga10b.h, - hal/fifo/fifo_intr_ga10b.h, - hal/fifo/fifo_ga10b.h ] - - channel_fusa: - safe: no - sources: [ hal/fifo/channel_ga10b_fusa.c, - hal/fifo/channel_ga10b.h, - hal/fifo/channel_ga100_fusa.c, - hal/fifo/channel_ga100.h ] - - tsg: - safe: no - sources: [ hal/fifo/tsg_ga10b.h, - hal/fifo/tsg_ga10b.c ] - - engine_status_fusa: - safe: no - sources: [ include/nvgpu/nvgpu_next_engine_status.h, - hal/fifo/engine_status_ga10b_fusa.c, - hal/fifo/engine_status_ga10b.h ] - - ramfc_fusa: - safe: no - sources: [ hal/fifo/ramfc_ga10b_fusa.c, - hal/fifo/ramfc_ga10b.h ] - - pbdma_status_fusa: - safe: no - sources: [ hal/fifo/pbdma_status_ga10b_fusa.c, - hal/fifo/pbdma_status_ga10b.h ] - - pbdma_fusa: - safe: no - sources: [ hal/fifo/pbdma_ga10b_fusa.c, - hal/fifo/pbdma_ga10b.h, - hal/fifo/pbdma_ga100_fusa.c, - hal/fifo/pbdma_ga100.h, - include/nvgpu/nvgpu_next_gops_pbdma.h ] - - preempt_fusa: - safe: no - sources: [ hal/fifo/preempt_ga10b_fusa.c, - hal/fifo/preempt_ga10b.h ] - pbdma: - safe: no - sources: [ hal/fifo/pbdma_ga10b.c ] - - ramin_fusa: - safe: no - sources: [ hal/fifo/ramin_ga10b_fusa.c, - hal/fifo/ramin_ga10b.h ] - - usermode_fusa: - safe: no - sources: [ hal/fifo/usermode_ga10b_fusa.c, - hal/fifo/usermode_ga10b.h ] - - userd: - safe: no - sources: [ hal/fifo/userd_ga10b.c, - hal/fifo/userd_ga10b.h ] - - utils_fusa: - safe: no - sources: [ hal/fifo/fifo_utils_ga10b_fusa.c, - hal/fifo/fifo_utils_ga10b.h ] -nvgpu_next_mm: - safe: no - owner: Seema K - children: - mm: - safe: no - sources: [ include/nvgpu/nvgpu_next_mm.h ] - mmu_fault: - safe: no - sources: [ hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c, - hal/mm/mmu_fault/mmu_fault_ga10b.h ] - - gmmu_fusa: - safe: no - sources: [ hal/mm/gmmu/gmmu_ga10b_fusa.c, - hal/mm/gmmu/gmmu_ga10b.h ] - -nvgpu_next_gr: - safe: no - owner: Seema K - children: - ctxsw_prog_fusa: - safe: no - sources: [ hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c, - hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h, - hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c, - hal/gr/ctxsw_prog/ctxsw_prog_ga100.h] - ctxsw_prog: - safe: no - sources: [ hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c, - hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c, - hal/gr/ctxsw_prog/ctxsw_prog_ga100.c, - hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c ] - - init_fusa: - safe: no - sources: [ include/nvgpu/nvgpu_next_gops_gr_init.h, - hal/gr/init/gr_init_ga10b_fusa.c, - hal/gr/init/gr_init_ga100_fusa.c, - hal/gr/init/gr_init_ga100.h, - hal/gr/init/gr_init_ga10b.h ] - - init: - safe: no - sources: [ hal/gr/init/gr_init_ga10b.c, - hal/gr/init/gr_init_ga10b.h, - hal/gr/init/gr_init_ga100.c, - hal/gr/init/gr_init_ga100.h ] - - intr_fusa: - safe: no - sources: [ include/nvgpu/nvgpu_next_gops_gr_intr.h, - hal/gr/intr/gr_intr_ga10b_fusa.c, - hal/gr/intr/gr_intr_ga10b.h, - hal/gr/intr/gr_intr_ga100_fusa.c, - hal/gr/intr/gr_intr_ga100.h ] - - gr: - safe: no - sources: [ hal/gr/gr/gr_ga10b.c, - hal/gr/gr/gr_ga10b.h, - hal/gr/gr/gr_ga100.c, - hal/gr/gr/gr_ga100.h, - hal/gr/gr/gr_pri_ga10b.h ] - - falcon_fusa: - safe: no - sources: [ hal/gr/falcon/gr_falcon_ga10b_fusa.c, - hal/gr/falcon/gr_falcon_ga10b.h ] - falcon: - safe: no - sources: [ hal/gr/falcon/gr_falcon_ga10b.c, - hal/gr/falcon/gr_falcon_ga100.c, - hal/gr/falcon/gr_falcon_ga100.h ] - - zbc: - safe: no - sources: [ hal/gr/zbc/zbc_ga10b.c, - hal/gr/zbc/zbc_ga10b.h ] - - ecc_fusa: - safe: no - sources: [ hal/gr/ecc/ecc_ga10b_fusa.c, - hal/gr/ecc/ecc_ga10b.h ] - - ecc: - safe: no - sources: [ hal/gr/ecc/ecc_ga10b.c , - hal/gr/ecc/ecc_ga10b.h ] - -nvgpu_next_ltc: - safe: no - owner: Vedashree V - children: - ltc: - safe: no - sources: [ hal/ltc/ltc_ga10b.c ] - - ltc_fusa: - safe: no - sources: [ hal/ltc/ltc_ga10b.h, - hal/ltc/ltc_ga10b_fusa.c ] - - ltc_intr: - safe: no - sources: [ hal/ltc/intr/ltc_intr_ga10b.h, - hal/ltc/intr/ltc_intr_ga10b_fusa.c ] - -nvgpu_next_mc_fusa: - safe: no - owner: Seema K - sources: [ hal/mc/mc_intr_ga10b_fusa.c, - include/nvgpu/nvgpu_next_mc.h, - hal/mc/mc_intr_ga10b.h, - include/nvgpu/nvgpu_next_gops_mc.h, - hal/mc/mc_ga10b_fusa.c, - hal/mc/mc_ga10b.h ] - -nvgpu_next_cbc: - safe: no - owner: Vedashree V - sources: [ hal/cbc/cbc_ga10b.c, - hal/cbc/cbc_ga10b.h, - hal/cbc/cbc_ga100.c, - hal/cbc/cbc_ga100.h ] - -nvgpu_next_fb: - safe: no - owner: Vedashree V - sources: [ hal/fb/fb_ga10b.c, - hal/fb/fb_ga100.h, - hal/fb/fb_ga100.c, - hal/fb/vab/vab_ga10b.c, - hal/fb/vab/vab_ga10b.h, - include/nvgpu/nvgpu_next_fb.h, - include/nvgpu/nvgpu_next_gops_fb_vab.h ] - -nvgpu_next_fb_fusa: - safe: no - owner: Seshendra G - sources: [ include/nvgpu/nvgpu_next_ecc.h, - hal/fb/fb_ga10b.h, - hal/fb/fb_ga10b_fusa.c, - include/nvgpu/nvgpu_next_gops_fb.h, - hal/fb/ecc/fb_ecc_ga10b.h, - hal/fb/ecc/fb_ecc_ga10b_fusa.c, - hal/fb/intr/fb_intr_ga10b.h, - hal/fb/intr/fb_intr_ga10b_fusa.c, - hal/fb/fb_mmu_fault_ga10b.h, - hal/fb/fb_mmu_fault_ga10b_fusa.c, - hal/fb/intr/fb_intr_ecc_ga10b.h, - hal/fb/intr/fb_intr_ecc_ga10b_fusa.c ] - -nvgpu_next_netlist: - safe: no - owner: Seshendra G - sources: [ hal/netlist/netlist_ga10b_fusa.c, - hal/netlist/netlist_ga10b.h, - hal/netlist/netlist_ga100.c, - hal/netlist/netlist_ga100.h ] - -nvgpu_next_bus: - safe: no - owner: Seshendra G - sources: [ hal/bus/bus_ga10b.c, - hal/bus/bus_ga10b.h, - hal/bus/bus_ga100.c, - hal/bus/bus_ga100.h ] - -nvgpu_next_regops: - safe: no - owner: Seshendra G - sources: [ hal/regops/regops_ga10b.c, - hal/regops/regops_ga100.c, - hal/regops/regops_ga10b.h, - hal/regops/regops_ga100.h, - hal/regops/allowlist_ga10b.c, - hal/regops/allowlist_ga10b.h, - hal/regops/allowlist_ga100.c, - hal/regops/allowlist_ga100.h ] - -nvgpu_next_falcon_fusa: - safe: no - owner: Divya S - sources: [ hal/falcon/falcon_ga10b_fusa.c, - hal/falcon/falcon_ga10b.h ] - -nvgpu_next_pmu: - safe: no - owner: Mahantesh K - sources: [ hal/pmu/pmu_ga10b.h, - hal/pmu/pmu_ga10b.c, - hal/pmu/pmu_ga100.h, - hal/pmu/pmu_ga100.c ] - -nvgpu_next_gsp: - safe: no - owner: Deepak G - sources: [ hal/gsp/gsp_ga10b.h, - hal/gsp/gsp_ga10b.c ] - -nvgpu_next_priv_ring_fusa: - safe: no - owner: Seema K - sources: [ hal/priv_ring/priv_ring_ga10b_fusa.c, - hal/priv_ring/priv_ring_ga10b.h, - hal/priv_ring/priv_ring_ga100_fusa.c, - hal/priv_ring/priv_ring_ga100.h ] - -nvgpu_next_ptimer_fusa: - safe: no - owner: Seema K - sources: [ hal/ptimer/ptimer_ga10b_fusa.c, - hal/ptimer/ptimer_ga10b.h ] - -nvgpu_next_perf: - safe: no - owner: Seshendra G - sources: [ hal/perf/perf_ga10b.c, - hal/perf/perf_ga10b.h, - hal/perf/perf_ga100.c, - hal/perf/perf_ga100.h, - include/nvgpu/nvgpu_next_gops_perf.h ] - -nvgpu_next_cg: - safe: no - owner: Antony - sources: [ include/nvgpu/nvgpu_next_gops_cg.h, - hal/power_features/cg/ga10b_gating_reglist.c, - hal/power_features/cg/ga10b_gating_reglist.h, - hal/power_features/cg/ga100_gating_reglist.c, - hal/power_features/cg/ga100_gating_reglist.h ] - -nvgpu_next_therm_fusa: - safe: no - owner: Antony - sources: [ hal/therm/therm_ga10b_fusa.c, - hal/therm/therm_ga10b.h ] - -nvgpu_next_ce_fusa: - safe: no - owner: Antony - sources: [ hal/ce/ce_ga10b_fusa.c, - hal/ce/ce_ga10b.h ] - -nvgpu_next_misc: - safe: no - owner: Vedashree V - sources: [ nvgpu_next_gpuid.h ] - -nvgpu_next_nvdec: - safe: no - owner: Mahantesh K - sources: [ hal/nvdec/nvdec_ga100.c, - hal/nvdec/nvdec_ga100.h ] - -nvgpu_next_grmgr: - safe: no - owner: Lakshmanan M - sources: [ hal/grmgr/grmgr_ga10b.c, - hal/grmgr/grmgr_ga10b.h, - hal/grmgr/grmgr_ga100.c, - hal/grmgr/grmgr_ga100.h,] - -nvgpu_next_func: - safe: no - owner: Vedashree V - sources: [ hal/func/func_ga10b.c, - hal/func/func_ga10b.h ] - diff --git a/arch/nvgpu-next-linux.yaml b/arch/nvgpu-next-linux.yaml deleted file mode 100644 index 4d2229883..000000000 --- a/arch/nvgpu-next-linux.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# - -# Linux elements and units in nvgpu. -# -# The safe: tag is ommited through out since all Linux units are by definition -# not safe. -# -# I also have not put a huge amount of thought into this since none of this -# code is "safe" code. Nor are we planning on spending a lot of effort to -# clean this up. At least not yet. - -nvgpu_next_platform: - sources: [ os/linux/platform_ga10b_tegra.c, - os/linux/nvlink/hal/ga10b_mssnvlink.c ] - -vgpu-next: - sources: [ os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c ] - -nvgpu_next_ioctl: - sources: [ os/linux/nvgpu_next_ioctl_prof.c, - os/linux/nvgpu_next_ioctl_prof.h ] diff --git a/arch/nvgpu.yaml b/arch/nvgpu.yaml index 2dca53bac..6fd27e89f 100644 --- a/arch/nvgpu.yaml +++ b/arch/nvgpu.yaml @@ -14,13 +14,13 @@ nvgpu: common: safe: no children: - !include nvgpu-common.yaml nvgpu-next-common.yaml + !include nvgpu-common.yaml # HAL units - Hardware Abstraction Layer. hal: safe: no children: - !include nvgpu-hal-new.yaml nvgpu-next-hal.yaml + !include nvgpu-hal-new.yaml # The QNX OS layer implementation units. qnx: @@ -32,7 +32,7 @@ nvgpu: linux: safe: no children: - !include nvgpu-linux.yaml nvgpu-next-linux.yaml + !include nvgpu-linux.yaml # POSIX units for implementing the OS layer for unit testing. posix: @@ -58,7 +58,7 @@ nvgpu: hal-vgpu: safe: yes children: - !include nvgpu-hal-vgpu.yaml nvgpu-next-hal-vgpu.yaml + !include nvgpu-hal-vgpu.yaml # A meta-element for the GPU HW. A good example of this is the HW headers. # This is not code we write in nvgpu, but we import it from the GPU HW @@ -66,4 +66,4 @@ nvgpu: gpu_hw: safe: no children: - !include nvgpu-gpu_hw.yaml nvgpu-next-gpu_hw.yaml + !include nvgpu-gpu_hw.yaml diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index acd8f25e3..f383eb1f8 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -790,23 +790,12 @@ endif ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),y) nvgpu-y += \ - common/fifo/nvgpu_next_engines.o \ - common/fifo/nvgpu_next_runlist.o \ - common/acr/nvgpu_next_acr_bootstrap.o \ common/falcon/falcon_sw_ga10b.o \ - common/fb/nvgpu_next_fb.o \ common/riscv/riscv.o \ common/acr/acr_sw_ga10b.o \ common/acr/acr_sw_ga100.o \ - common/sim/nvgpu_next_sim.o \ - common/gr/nvgpu_next_gr.o \ - common/gr/nvgpu_next_fs_state.o \ - common/netlist/nvgpu_next_netlist.o \ - common/sim/nvgpu_next_sim_netlist.o \ common/pmu/perfmon/pmu_perfmon_sw_ga10b.o \ - common/cic/nvgpu_next_cic.o \ - common/pmu/pg/pg_sw_ga10b.o \ - common/profiler/nvgpu_next_profiler.o + common/pmu/pg/pg_sw_ga10b.o nvgpu-y += \ hal/init/hal_ga10b.o \ @@ -929,5 +918,4 @@ endif nvgpu-y += \ os/linux/platform_ga10b_tegra.o \ - os/linux/nvgpu_next_ioctl_prof.o \ os/linux/nvlink/hal/ga10b_mssnvlink.o diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 51a532e0c..a47956a16 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -712,23 +712,12 @@ endif ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1) srcs += \ - common/fifo/nvgpu_next_engines.c \ - common/acr/nvgpu_next_acr_bootstrap.c \ common/riscv/riscv.c \ common/acr/acr_sw_ga10b.c \ common/acr/acr_sw_ga100.c \ - common/fb/nvgpu_next_fb.c \ - common/fifo/nvgpu_next_runlist.c \ - common/gr/nvgpu_next_gr.c \ - common/gr/nvgpu_next_fs_state.c \ - common/netlist/nvgpu_next_netlist.c \ - common/sim/nvgpu_next_sim.c \ - common/sim/nvgpu_next_sim_netlist.c \ common/pmu/perfmon/pmu_perfmon_sw_ga10b.c \ - common/cic/nvgpu_next_cic.c \ common/pmu/pg/pg_sw_ga10b.c \ common/falcon/falcon_sw_ga10b.c \ - common/profiler/nvgpu_next_profiler.c srcs += hal/init/hal_ga10b.c \ hal/init/hal_ga10b_litter.c \ diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c index 1116a9bb0..ec96c1919 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c @@ -31,6 +31,10 @@ #include #include #include +#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) +#include +#include +#endif #include "acr_bootstrap.h" #include "acr_priv.h" @@ -252,3 +256,135 @@ err_free_ucode: acr_desc->acr_fw = NULL; return err; } + +#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) +#define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS 10000 /*in msec */ +#define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS 100 /*in msec */ + +static void ga10b_riscv_release_firmware(struct gk20a *g, struct nvgpu_acr *acr) +{ + nvgpu_release_firmware(g, acr->acr_asc.manifest_fw); + nvgpu_release_firmware(g, acr->acr_asc.code_fw); + nvgpu_release_firmware(g, acr->acr_asc.data_fw); +} + +static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr) +{ + int err = 0; + + acr->manifest_fw = nvgpu_request_firmware(g, + acr->acr_manifest_name, + NVGPU_REQUEST_FIRMWARE_NO_WARN); + if (acr->manifest_fw == NULL) { + nvgpu_err(g, "%s ucode get fail for %s", + acr->acr_manifest_name, g->name); + return -ENOENT; + } + + acr->code_fw = nvgpu_request_firmware(g, + acr->acr_code_name, + NVGPU_REQUEST_FIRMWARE_NO_WARN); + if (acr->code_fw == NULL) { + nvgpu_err(g, "%s ucode get fail for %s", + acr->acr_code_name, g->name); + nvgpu_release_firmware(g, acr->manifest_fw); + return -ENOENT; + } + + acr->data_fw = nvgpu_request_firmware(g, + acr->acr_data_name, + NVGPU_REQUEST_FIRMWARE_NO_WARN); + if (acr->data_fw == NULL) { + nvgpu_err(g, "%s ucode get fail for %s", + acr->acr_data_name, g->name); + nvgpu_release_firmware(g, acr->manifest_fw); + nvgpu_release_firmware(g, acr->code_fw); + return -ENOENT; + } + + return err; +} + +static bool nvgpu_acr_wait_for_riscv_brom_completion(struct nvgpu_falcon *flcn, + signed int timeoutms) +{ + u32 reg = 0; + + do { + reg = flcn->g->ops.falcon.get_brom_retcode(flcn); + if (flcn->g->ops.falcon.check_brom_passed(reg)) { + break; + } + + if (timeoutms <= 0) { + return false; + } + + nvgpu_msleep(10); + timeoutms -= 10; + + } while (true); + + return true; +} + +int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr) +{ + int err = 0; + bool brom_complete = false; + u32 timeout = 0; + u64 acr_sysmem_desc_addr = 0LL; + + err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc); + if (err !=0) { + nvgpu_err(g, "RISCV ucode loading failed"); + return -EINVAL; + } + + err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false); + if (err != 0) { + nvgpu_err(g, "RISCV ucode patch wpr info failed"); + return err; + } + + acr_sysmem_desc_addr = nvgpu_mem_get_addr(g, + &acr->acr_asc.acr_falcon2_sysmem_desc); + + nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn); + + nvgpu_riscv_hs_ucode_load_bootstrap(acr->acr_asc.acr_flcn, + acr->acr_asc.manifest_fw, + acr->acr_asc.code_fw, + acr->acr_asc.data_fw, + acr_sysmem_desc_addr); + + if (nvgpu_platform_is_silicon(g)) { + timeout = RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS; + } else { + timeout = RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS; + } + brom_complete = nvgpu_acr_wait_for_riscv_brom_completion( + acr->acr_asc.acr_flcn, timeout); + + nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn); + + if (brom_complete == false) { + nvgpu_err(g, "RISCV BROM timed out, limit: %d ms", timeout); + err = -ETIMEDOUT; + } else { + nvgpu_info(g, "RISCV BROM passed"); + } + + /* wait for complete & halt */ + if (nvgpu_platform_is_silicon(g)) { + timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS; + } else { + timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS; + } + err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout); + + ga10b_riscv_release_firmware(g, acr); + + return err; +} +#endif diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h index 7dd5d1282..f63199ecd 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h @@ -24,12 +24,10 @@ #define ACR_BOOTSTRAP_H #include "nvgpu_acr_interface.h" -#ifdef CONFIG_NVGPU_NON_FUSA -#include "common/acr/nvgpu_next_acr_bootstrap.h" -#endif struct gk20a; struct nvgpu_acr; +struct hs_acr; struct flcn_acr_region_prop_v0 { u32 start_addr; @@ -136,4 +134,9 @@ int nvgpu_acr_wait_for_completion(struct gk20a *g, struct hs_acr *acr_desc, int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_desc); + +#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) +int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr); +#endif + #endif /* ACR_BOOTSTRAP_H */ diff --git a/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c deleted file mode 100644 index 11268015c..000000000 --- a/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common/acr/acr_bootstrap.h" -#include "common/acr/acr_priv.h" - -#define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS 10000 /*in msec */ -#define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS 100 /*in msec */ - -static void ga10b_riscv_release_firmware(struct gk20a *g, struct nvgpu_acr *acr) -{ - nvgpu_release_firmware(g, acr->acr_asc.manifest_fw); - nvgpu_release_firmware(g, acr->acr_asc.code_fw); - nvgpu_release_firmware(g, acr->acr_asc.data_fw); -} - -static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr) -{ - int err = 0; - - acr->manifest_fw = nvgpu_request_firmware(g, - acr->acr_manifest_name, - NVGPU_REQUEST_FIRMWARE_NO_WARN); - if (acr->manifest_fw == NULL) { - nvgpu_err(g, "%s ucode get fail for %s", - acr->acr_manifest_name, g->name); - return -ENOENT; - } - - acr->code_fw = nvgpu_request_firmware(g, - acr->acr_code_name, - NVGPU_REQUEST_FIRMWARE_NO_WARN); - if (acr->code_fw == NULL) { - nvgpu_err(g, "%s ucode get fail for %s", - acr->acr_code_name, g->name); - nvgpu_release_firmware(g, acr->manifest_fw); - return -ENOENT; - } - - acr->data_fw = nvgpu_request_firmware(g, - acr->acr_data_name, - NVGPU_REQUEST_FIRMWARE_NO_WARN); - if (acr->data_fw == NULL) { - nvgpu_err(g, "%s ucode get fail for %s", - acr->acr_data_name, g->name); - nvgpu_release_firmware(g, acr->manifest_fw); - nvgpu_release_firmware(g, acr->code_fw); - return -ENOENT; - } - - return err; -} - -static bool nvgpu_acr_wait_for_riscv_brom_completion(struct nvgpu_falcon *flcn, - signed int timeoutms) -{ - u32 reg = 0; - - do { - reg = flcn->g->ops.falcon.get_brom_retcode(flcn); - if (flcn->g->ops.falcon.check_brom_passed(reg)) { - break; - } - - if (timeoutms <= 0) { - return false; - } - - nvgpu_msleep(10); - timeoutms -= 10; - - } while (true); - - return true; -} - -int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr) -{ - int err = 0; - bool brom_complete = false; - u32 timeout = 0; - u64 acr_sysmem_desc_addr = 0LL; - - err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc); - if (err !=0) { - nvgpu_err(g, "RISCV ucode loading failed"); - return -EINVAL; - } - - err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false); - if (err != 0) { - nvgpu_err(g, "RISCV ucode patch wpr info failed"); - return err; - } - - acr_sysmem_desc_addr = nvgpu_mem_get_addr(g, - &acr->acr_asc.acr_falcon2_sysmem_desc); - - nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn); - - nvgpu_riscv_hs_ucode_load_bootstrap(acr->acr_asc.acr_flcn, - acr->acr_asc.manifest_fw, - acr->acr_asc.code_fw, - acr->acr_asc.data_fw, - acr_sysmem_desc_addr); - - if (nvgpu_platform_is_silicon(g)) { - timeout = RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS; - } else { - timeout = RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS; - } - brom_complete = nvgpu_acr_wait_for_riscv_brom_completion( - acr->acr_asc.acr_flcn, timeout); - - nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn); - - if (brom_complete == false) { - nvgpu_err(g, "RISCV BROM timed out, limit: %d ms", timeout); - err = -ETIMEDOUT; - } else { - nvgpu_info(g, "RISCV BROM passed"); - } - - /* wait for complete & halt */ - if (nvgpu_platform_is_silicon(g)) { - timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS; - } else { - timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS; - } - err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout); - - ga10b_riscv_release_firmware(g, acr); - - return err; -} diff --git a/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h b/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h deleted file mode 100644 index 747773194..000000000 --- a/drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_ACR_BOOTSTRAP_H -#define NVGPU_NEXT_ACR_BOOTSTRAP_H - -struct gk20a; -struct nvgpu_acr; -struct hs_acr; - -int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr); - -#endif /* NVGPU_NEXT_ACR_BOOTSTRAP_H */ diff --git a/drivers/gpu/nvgpu/common/cic/cic.c b/drivers/gpu/nvgpu/common/cic/cic.c index 12d3877aa..2ab8c62fa 100644 --- a/drivers/gpu/nvgpu/common/cic/cic.c +++ b/drivers/gpu/nvgpu/common/cic/cic.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -159,3 +160,71 @@ int nvgpu_cic_get_num_hw_modules(struct gk20a *g) return g->cic->num_hw_modules; } + +#if defined(CONFIG_NVGPU_NON_FUSA) +void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid, + u32 num_entries) +{ + unsigned long flags = 0; + u32 i = 0U; + struct nvgpu_intr_unit_info *intr_unit_info; + + nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX); + + nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries); + + intr_unit_info = g->mc.nvgpu_next.intr_unit_info; + + nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags); + + if (intr_unit_info[unit].valid == false) { + for (i = 0U; i < num_entries; i++) { + nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i, + *(vectorid + i)); + intr_unit_info[unit].vectorid[i] = *(vectorid + i); + } + intr_unit_info[unit].vectorid_size = num_entries; + } + nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); +} + +bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit) +{ + struct nvgpu_intr_unit_info *intr_unit_info; + bool info_valid = false; + + if (unit >= NVGPU_CIC_INTR_UNIT_MAX) { + nvgpu_err(g, "invalid unit(%d)", unit); + return false; + } + + intr_unit_info = g->mc.nvgpu_next.intr_unit_info; + + if (intr_unit_info[unit].valid == true) { + info_valid = true; + } + + return info_valid; +} + +bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree, + u64 *subtree_mask) +{ + if (unit >= NVGPU_CIC_INTR_UNIT_MAX) { + nvgpu_err(g, "invalid unit(%d)", unit); + return false; + } + if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) { + if (g->ops.mc.intr_get_unit_info(g, unit) != true) { + nvgpu_err(g, "failed to fetch info for unit(%d)", unit); + return false; + } + } + *subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree; + *subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask; + nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)", + *subtree, *subtree_mask); + + return true; +} +#endif diff --git a/drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c b/drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c deleted file mode 100644 index 9dfeec9be..000000000 --- a/drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid, - u32 num_entries) -{ - unsigned long flags = 0; - u32 i = 0U; - struct nvgpu_intr_unit_info *intr_unit_info; - - nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX); - - nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries); - - intr_unit_info = g->mc.nvgpu_next.intr_unit_info; - - nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags); - - if (intr_unit_info[unit].valid == false) { - for (i = 0U; i < num_entries; i++) { - nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i, - *(vectorid + i)); - intr_unit_info[unit].vectorid[i] = *(vectorid + i); - } - intr_unit_info[unit].vectorid_size = num_entries; - } - nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); -} - -bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit) -{ - struct nvgpu_intr_unit_info *intr_unit_info; - bool info_valid = false; - - if (unit >= NVGPU_CIC_INTR_UNIT_MAX) { - nvgpu_err(g, "invalid unit(%d)", unit); - return false; - } - - intr_unit_info = g->mc.nvgpu_next.intr_unit_info; - - if (intr_unit_info[unit].valid == true) { - info_valid = true; - } - - return info_valid; -} - -bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree, - u64 *subtree_mask) -{ - if (unit >= NVGPU_CIC_INTR_UNIT_MAX) { - nvgpu_err(g, "invalid unit(%d)", unit); - return false; - } - if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) { - if (g->ops.mc.intr_get_unit_info(g, unit) != true) { - nvgpu_err(g, "failed to fetch info for unit(%d)", unit); - return false; - } - } - *subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree; - *subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask; - nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)", - *subtree, *subtree_mask); - - return true; -} diff --git a/drivers/gpu/nvgpu/common/fb/fb.c b/drivers/gpu/nvgpu/common/fb/fb.c index d82568589..4cde5503d 100644 --- a/drivers/gpu/nvgpu/common/fb/fb.c +++ b/drivers/gpu/nvgpu/common/fb/fb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -39,3 +39,25 @@ int nvgpu_init_fb_support(struct gk20a *g) } return 0; } + +#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) +int nvgpu_fb_vab_init_hal(struct gk20a *g) +{ + int err = 0; + + if (g->ops.fb.vab.init != NULL) { + err = g->ops.fb.vab.init(g); + } + return err; +} + +int nvgpu_fb_vab_teardown_hal(struct gk20a *g) +{ + int err = 0; + + if (g->ops.fb.vab.teardown != NULL) { + err = g->ops.fb.vab.teardown(g); + } + return err; +} +#endif diff --git a/drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c b/drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c deleted file mode 100644 index 7e9b76c17..000000000 --- a/drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -int nvgpu_fb_vab_init_hal(struct gk20a *g) -{ - int err = 0; - - if (g->ops.fb.vab.init != NULL) { - err = g->ops.fb.vab.init(g); - } - return err; -} - -int nvgpu_fb_vab_teardown_hal(struct gk20a *g) -{ - int err = 0; - - if (g->ops.fb.vab.teardown != NULL) { - err = g->ops.fb.vab.teardown(g); - } - return err; -} \ No newline at end of file diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 06a8517fc..45e712004 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -706,6 +706,61 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg) return engines; } + +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +int nvgpu_next_engine_init_one_dev(struct gk20a *g, + const struct nvgpu_device *dev) +{ + struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev; + + /* + * Currently due to the nature of the nvgpu_next repo, this will still + * be called even on non-ga10b systems. Eventually this code will fold into + * the nvgpu-linux repo, at which point this logic will be present in + * nvgpu_engine_init_one_dev(). + * + * In any event, the purpose of this is to make sure we _don't_ execute + * this code pre-ga10b. We can check for HALs that only exist on ga10x to + * short circuit. + */ + if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) { + return 0; + } + + /* + * Init PBDMA info for this device; needs FIFO to be alive to do this. + * SW expects at least pbdma instance0 to be valid. + * + * See JIRA NVGPU-4980 for multiple pbdma support. + */ + g->ops.runlist.get_pbdma_info(g, + dev->next.rl_pri_base, + &dev_rw->next.pbdma_info); + if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] == + NVGPU_INVALID_PBDMA_ID) { + nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d", + dev->engine_id); + return -EINVAL; + } + + dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0]; + + nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id); + nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u", + dev->inst_id, dev->runlist_id, dev->fault_id); + nvgpu_log(g, gpu_dbg_device, " intr_id %u, reset_id %u", + dev->intr_id, dev->reset_id); + nvgpu_log(g, gpu_dbg_device, " engine_type %u", + dev->type); + nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x", + dev->reset_id, dev->next.rleng_id); + nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x", + dev->next.rl_pri_base); + + return 0; +} +#endif + static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f, const struct nvgpu_device *dev) { diff --git a/drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c b/drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c deleted file mode 100644 index a7141c027..000000000 --- a/drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -int nvgpu_next_engine_init_one_dev(struct gk20a *g, - const struct nvgpu_device *dev) -{ - struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev; - - /* - * Currently due to the nature of the nvgpu_next repo, this will still - * be called even on non-ga10b systems. Eventually this code will fold into - * the nvgpu-linux repo, at which point this logic will be present in - * nvgpu_engine_init_one_dev(). - * - * In any event, the purpose of this is to make sure we _don't_ execute - * this code pre-ga10b. We can check for HALs that only exist on ga10x to - * short circuit. - */ - if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) { - return 0; - } - - /* - * Init PBDMA info for this device; needs FIFO to be alive to do this. - * SW expects at least pbdma instance0 to be valid. - * - * See JIRA NVGPU-4980 for multiple pbdma support. - */ - g->ops.runlist.get_pbdma_info(g, - dev->next.rl_pri_base, - &dev_rw->next.pbdma_info); - if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] == - NVGPU_INVALID_PBDMA_ID) { - nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d", - dev->engine_id); - return -EINVAL; - } - - dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0]; - - nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id); - nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u", - dev->inst_id, dev->runlist_id, dev->fault_id); - nvgpu_log(g, gpu_dbg_device, " intr_id %u, reset_id %u", - dev->intr_id, dev->reset_id); - nvgpu_log(g, gpu_dbg_device, " engine_type %u", - dev->type); - nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x", - dev->reset_id, dev->next.rleng_id); - nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x", - dev->next.rl_pri_base); - - return 0; -} diff --git a/drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c b/drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c deleted file mode 100644 index 6ec71fdba..000000000 --- a/drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -static void nvgpu_runlist_init_engine_info(struct gk20a *g, - struct nvgpu_runlist *runlist, - const struct nvgpu_device *dev) -{ - u32 i = 0U; - - /* - * runlist_pri_base, chram_bar0_offset and pbdma_info - * will get over-written with same info, if multiple engines - * are present on same runlist. Required optimization will be - * done as part of JIRA NVGPU-4980 - */ - runlist->nvgpu_next.runlist_pri_base = - dev->next.rl_pri_base; - runlist->nvgpu_next.chram_bar0_offset = - g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base); - - nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x", - runlist->id, runlist->nvgpu_next.runlist_pri_base); - nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x", - runlist->id, runlist->nvgpu_next.chram_bar0_offset); - - runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info; - for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { - nvgpu_log(g, gpu_dbg_info, - "runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x", - runlist->id, i, - runlist->nvgpu_next.pbdma_info->pbdma_id[i], i, - runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]); - } - - runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev; -} - -static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g, - struct nvgpu_runlist *runlist) -{ - u32 pbdma_mask = 0U; - u32 i; - u32 pbdma_id; - - nvgpu_assert(runlist != NULL); - - for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { - pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i]; - if (pbdma_id != NVGPU_INVALID_PBDMA_ID) - pbdma_mask |= BIT32(pbdma_id); - } - return pbdma_mask; -} - -void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f) -{ - struct nvgpu_runlist *runlist; - const struct nvgpu_device *dev; - u32 i, j; - - nvgpu_log_fn(g, " "); - - if (g->is_virtual) { - return; - } - - for (i = 0U; i < f->num_runlists; i++) { - runlist = &f->active_runlists[i]; - - nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i); - - for (j = 0U; j < f->num_engines; j++) { - dev = f->active_engines[j]; - - if (dev->runlist_id == runlist->id) { - runlist->eng_bitmask |= BIT32(dev->engine_id); - nvgpu_runlist_init_engine_info(g, runlist, dev); - } - } - - runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist); - - nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask); - nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask); - } - - nvgpu_log_fn(g, "done"); -} diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c index 809695402..ff532c018 100644 --- a/drivers/gpu/nvgpu/common/fifo/runlist.c +++ b/drivers/gpu/nvgpu/common/fifo/runlist.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -912,3 +913,92 @@ void nvgpu_runlist_unlock_runlists(struct gk20a *g, u32 runlists_mask) } } } + +#if defined(CONFIG_NVGPU_NON_FUSA) +static void nvgpu_runlist_init_engine_info(struct gk20a *g, + struct nvgpu_runlist *runlist, + const struct nvgpu_device *dev) +{ + u32 i = 0U; + + /* + * runlist_pri_base, chram_bar0_offset and pbdma_info + * will get over-written with same info, if multiple engines + * are present on same runlist. Required optimization will be + * done as part of JIRA NVGPU-4980 + */ + runlist->nvgpu_next.runlist_pri_base = + dev->next.rl_pri_base; + runlist->nvgpu_next.chram_bar0_offset = + g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base); + + nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x", + runlist->id, runlist->nvgpu_next.runlist_pri_base); + nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x", + runlist->id, runlist->nvgpu_next.chram_bar0_offset); + + runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info; + for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { + nvgpu_log(g, gpu_dbg_info, + "runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x", + runlist->id, i, + runlist->nvgpu_next.pbdma_info->pbdma_id[i], i, + runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]); + } + + runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev; +} + +static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g, + struct nvgpu_runlist *runlist) +{ + u32 pbdma_mask = 0U; + u32 i; + u32 pbdma_id; + + nvgpu_assert(runlist != NULL); + + for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { + pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i]; + if (pbdma_id != NVGPU_INVALID_PBDMA_ID) + pbdma_mask |= BIT32(pbdma_id); + } + return pbdma_mask; +} + +void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f) +{ + struct nvgpu_runlist *runlist; + const struct nvgpu_device *dev; + u32 i, j; + + nvgpu_log_fn(g, " "); + + if (g->is_virtual) { + return; + } + + for (i = 0U; i < f->num_runlists; i++) { + runlist = &f->active_runlists[i]; + + nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i); + + for (j = 0U; j < f->num_engines; j++) { + dev = f->active_engines[j]; + + if (dev->runlist_id == runlist->id) { + runlist->eng_bitmask |= BIT32(dev->engine_id); + nvgpu_runlist_init_engine_info(g, runlist, dev); + } + } + + runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist); + + nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask); + nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask); + } + + nvgpu_log_fn(g, "done"); +} +#endif + diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c index d6b2e0f91..cb976d543 100644 --- a/drivers/gpu/nvgpu/common/gr/fs_state.c +++ b/drivers/gpu/nvgpu/common/gr/fs_state.c @@ -194,3 +194,35 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config) return err; } +#ifdef CONFIG_NVGPU_HAL_NON_FUSA +int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config) +{ + u32 tpc_index, gpc_index; + u32 sm_id = 0; + u32 num_sm; + int err = 0; + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " "); + + err = g->ops.gr.config.init_sm_id_table(g, config); + if (err != 0) { + return err; + } + + num_sm = nvgpu_gr_config_get_no_of_sm(config); + nvgpu_assert(num_sm > 0U); + + for (sm_id = 0; sm_id < num_sm; sm_id++) { + struct nvgpu_sm_info *sm_info = + nvgpu_gr_config_get_sm_info(config, sm_id); + tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info); + gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info); + + g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id, + config, NULL, false); + } + + return err; +} +#endif + diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 99a1c1340..7702413b6 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -561,8 +561,8 @@ static int gr_init_prepare_hw_impl(struct gk20a *g) } #if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(g); - nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(g); + nvgpu_gr_init_reset_enable_hw_non_ctx_local(g); + nvgpu_gr_init_reset_enable_hw_non_ctx_global(g); #endif nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes"); @@ -1200,3 +1200,59 @@ u32 nvgpu_gr_get_tpc_num(struct gk20a *g, u32 addr) } return 0; } + +#ifdef CONFIG_NVGPU_NON_FUSA +void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g) +{ + u32 i = 0U; + struct netlist_av_list *sw_non_ctx_local_compute_load = + nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); +#ifdef CONFIG_NVGPU_GRAPHICS + struct netlist_av_list *sw_non_ctx_local_gfx_load = + nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); +#endif + + for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) { + nvgpu_writel(g, sw_non_ctx_local_compute_load->l[i].addr, + sw_non_ctx_local_compute_load->l[i].value); + } + +#ifdef CONFIG_NVGPU_GRAPHICS + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { + for (i = 0U; i < sw_non_ctx_local_gfx_load->count; i++) { + nvgpu_writel(g, sw_non_ctx_local_gfx_load->l[i].addr, + sw_non_ctx_local_gfx_load->l[i].value); + } + } +#endif + + return; +} + +void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g) +{ + u32 i = 0U; + struct netlist_av_list *sw_non_ctx_global_compute_load = + nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); +#ifdef CONFIG_NVGPU_GRAPHICS + struct netlist_av_list *sw_non_ctx_global_gfx_load = + nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); +#endif + + for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) { + nvgpu_writel(g, sw_non_ctx_global_compute_load->l[i].addr, + sw_non_ctx_global_compute_load->l[i].value); + } + +#ifdef CONFIG_NVGPU_GRAPHICS + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { + for (i = 0U; i < sw_non_ctx_global_gfx_load->count; i++) { + nvgpu_writel(g, sw_non_ctx_global_gfx_load->l[i].addr, + sw_non_ctx_global_gfx_load->l[i].value); + } + } +#endif + + return; +} +#endif diff --git a/drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c b/drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c deleted file mode 100644 index d756f3ee6..000000000 --- a/drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include -#include - -int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config) -{ - u32 tpc_index, gpc_index; - u32 sm_id = 0; - u32 num_sm; - int err = 0; - - nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " "); - - err = g->ops.gr.config.init_sm_id_table(g, config); - if (err != 0) { - return err; - } - - num_sm = nvgpu_gr_config_get_no_of_sm(config); - nvgpu_assert(num_sm > 0U); - - for (sm_id = 0; sm_id < num_sm; sm_id++) { - struct nvgpu_sm_info *sm_info = - nvgpu_gr_config_get_sm_info(config, sm_id); - tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info); - gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info); - - g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id, - config, NULL, false); - } - - return err; -} diff --git a/drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c b/drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c deleted file mode 100644 index 7595176d9..000000000 --- a/drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include - -void nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g) -{ - u32 i = 0U; - struct netlist_av_list *sw_non_ctx_local_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); -#ifdef CONFIG_NVGPU_GRAPHICS - struct netlist_av_list *sw_non_ctx_local_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); -#endif - - for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) { - nvgpu_writel(g, sw_non_ctx_local_compute_load->l[i].addr, - sw_non_ctx_local_compute_load->l[i].value); - } - -#ifdef CONFIG_NVGPU_GRAPHICS - if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { - for (i = 0U; i < sw_non_ctx_local_gfx_load->count; i++) { - nvgpu_writel(g, sw_non_ctx_local_gfx_load->l[i].addr, - sw_non_ctx_local_gfx_load->l[i].value); - } - } -#endif - - return; -} - -void nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g) -{ - u32 i = 0U; - struct netlist_av_list *sw_non_ctx_global_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); -#ifdef CONFIG_NVGPU_GRAPHICS - struct netlist_av_list *sw_non_ctx_global_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); -#endif - - for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) { - nvgpu_writel(g, sw_non_ctx_global_compute_load->l[i].addr, - sw_non_ctx_global_compute_load->l[i].value); - } - -#ifdef CONFIG_NVGPU_GRAPHICS - if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { - for (i = 0U; i < sw_non_ctx_global_gfx_load->count; i++) { - nvgpu_writel(g, sw_non_ctx_global_gfx_load->l[i].addr, - sw_non_ctx_global_gfx_load->l[i].value); - } - } -#endif - - return; -} diff --git a/drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c b/drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c deleted file mode 100644 index 01a242bd5..000000000 --- a/drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -void nvgpu_mc_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid, - u32 num_entries) -{ - unsigned long flags = 0; - u32 i = 0U; - struct nvgpu_intr_unit_info *intr_unit_info; - - nvgpu_assert(num_entries <= MC_INTR_VECTORID_SIZE_MAX); - - nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries); - - intr_unit_info = g->mc.nvgpu_next.intr_unit_info; - - nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags); - - if (intr_unit_info[unit].valid == false) { - for (i = 0U; i < num_entries; i++) { - nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i, - *(vectorid + i)); - intr_unit_info[unit].vectorid[i] = *(vectorid + i); - } - intr_unit_info[unit].vectorid_size = num_entries; - } - nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); -} - -bool nvgpu_mc_intr_is_unit_info_valid(struct gk20a *g, u32 unit) -{ - struct nvgpu_intr_unit_info *intr_unit_info; - bool info_valid = false; - - if (unit >= MC_INTR_UNIT_MAX) { - nvgpu_err(g, "invalid unit(%d)", unit); - return false; - } - - intr_unit_info = g->mc.nvgpu_next.intr_unit_info; - - if (intr_unit_info[unit].valid == true) { - info_valid = true; - } - - return info_valid; -} - -bool nvgpu_mc_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree, - u64 *subtree_mask) -{ - if (unit >= MC_INTR_UNIT_MAX) { - nvgpu_err(g, "invalid unit(%d)", unit); - return false; - } - if (nvgpu_mc_intr_is_unit_info_valid(g, unit) != true) { - if (g->ops.mc.intr_get_unit_info(g, unit) != true) { - nvgpu_err(g, "failed to fetch info for unit(%d)", unit); - return false; - } - } - *subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree; - *subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask; - nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)", - *subtree, *subtree_mask); - - return true; -} diff --git a/drivers/gpu/nvgpu/common/netlist/netlist.c b/drivers/gpu/nvgpu/common/netlist/netlist.c index 920ef4050..a30e3bafb 100644 --- a/drivers/gpu/nvgpu/common/netlist/netlist.c +++ b/drivers/gpu/nvgpu/common/netlist/netlist.c @@ -31,9 +31,6 @@ #include #include #include -#if defined(CONFIG_NVGPU_NON_FUSA) -#include "nvgpu/nvgpu_next_netlist.h" -#endif #include "netlist_priv.h" #include "netlist_defs.h" @@ -1074,4 +1071,333 @@ void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index) { g->netlist_vars->regs_base_index = index; } + +#ifdef CONFIG_NVGPU_DEBUGGER +bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g, + u32 region_id, u8 *src, u32 size, + struct nvgpu_netlist_vars *netlist_vars, int *err_code) +{ + int err = 0; + bool handled = true; + + switch (region_id) { + case NETLIST_REGIONID_CTXREG_SYS_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.sys_compute); + break; + case NETLIST_REGIONID_CTXREG_GPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute); + break; + case NETLIST_REGIONID_CTXREG_TPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute); + break; + case NETLIST_REGIONID_CTXREG_PPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute); + break; + case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute); + break; + case NETLIST_REGIONID_CTXREG_LTS_BC: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.lts_bc); + break; + case NETLIST_REGIONID_CTXREG_LTS_UC: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.lts_uc); + break; + default: + handled = false; + break; + } + + if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) { + handled = true; + switch (region_id) { +#ifdef CONFIG_NVGPU_GRAPHICS + case NETLIST_REGIONID_CTXREG_SYS_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx); + break; + case NETLIST_REGIONID_CTXREG_GPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx); + break; + case NETLIST_REGIONID_CTXREG_TPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx); + break; + case NETLIST_REGIONID_CTXREG_PPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx); + break; + case NETLIST_REGIONID_CTXREG_ETPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx); + break; +#endif + default: + handled = false; + break; + } + } + *err_code = err; + + return handled; +} + +void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g) +{ + struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars; + + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l); +} +#endif /* CONFIG_NVGPU_DEBUGGER */ + +bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g, + u32 region_id, u8 *src, u32 size, + struct nvgpu_netlist_vars *netlist_vars, int *err_code) +{ + int err = 0; + bool handled = true; + + switch(region_id) { + case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load); + break; + case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load); + break; + default: + handled = false; + break; + } + + if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) { + handled = true; + switch (region_id) { +#ifdef CONFIG_NVGPU_GRAPHICS + case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load); + break; + case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load); + break; +#endif + default: + handled = false; + break; + } + } + *err_code = err; + + return handled; +} + +void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g) +{ + struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars; + + nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l); + nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l); +#ifdef CONFIG_NVGPU_GRAPHICS + nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l); + nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l); +#endif +} + +#ifdef CONFIG_NVGPU_DEBUGGER +struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx; +} + +struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx; +} + +u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g) +{ + u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count; + + count = nvgpu_safe_add_u32(count, + nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count); + return count; +} + +u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g) +{ + u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count; + + count = nvgpu_safe_add_u32(count, + nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count); + return count; +} + +u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g) +{ + u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count; + + count = nvgpu_safe_add_u32(count, + nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count); + return count; +} + +u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g) +{ + u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count; + + count = nvgpu_safe_add_u32(count, + nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count); + return count; +} + +u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g) +{ + u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count; + + count = nvgpu_safe_add_u32(count, + nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count); + return count; +} + +void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g) +{ + nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d", + nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count, + nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", + nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count, + nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", + nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count, + nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d", + nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count, + nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", + nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count, + nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d", + nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count); +} +#endif /* CONFIG_NVGPU_DEBUGGER */ + +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list( + struct gk20a *g) +{ + return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load; +} + +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list( + struct gk20a *g) +{ + return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load; +} + +#ifdef CONFIG_NVGPU_GRAPHICS +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list( + struct gk20a *g) +{ + return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load; +} + +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list( + struct gk20a *g) +{ + return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load; +} +#endif /* CONFIG_NVGPU_GRAPHICS */ + #endif diff --git a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h index efd7fc71b..5d7dfabd6 100644 --- a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h +++ b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h @@ -25,10 +25,6 @@ #include -#if defined(CONFIG_NVGPU_NON_FUSA) -#include "common/netlist/nvgpu_next_netlist_priv.h" -#endif - struct netlist_u32_list; struct netlist_av_list; struct netlist_av64_list; @@ -78,10 +74,30 @@ struct netlist_aiv_list; #define NETLIST_REGIONID_SW_BUNDLE64_INIT 34 #ifdef CONFIG_NVGPU_DEBUGGER #define NETLIST_REGIONID_NVPERF_PMCAU 35 +#define NETLIST_REGIONID_CTXREG_SYS_COMPUTE 36 +#define NETLIST_REGIONID_CTXREG_GPC_COMPUTE 38 +#define NETLIST_REGIONID_CTXREG_TPC_COMPUTE 40 +#define NETLIST_REGIONID_CTXREG_PPC_COMPUTE 42 +#define NETLIST_REGIONID_CTXREG_ETPC_COMPUTE 44 +#ifdef CONFIG_NVGPU_GRAPHICS +#define NETLIST_REGIONID_CTXREG_SYS_GFX 37 +#define NETLIST_REGIONID_CTXREG_GPC_GFX 39 +#define NETLIST_REGIONID_CTXREG_TPC_GFX 41 +#define NETLIST_REGIONID_CTXREG_PPC_GFX 43 +#define NETLIST_REGIONID_CTXREG_ETPC_GFX 45 +#endif /* CONFIG_NVGPU_GRAPHICS */ +#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD 48 +#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD 50 +#ifdef CONFIG_NVGPU_GRAPHICS +#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD 49 +#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD 51 +#endif /* CONFIG_NVGPU_GRAPHICS */ #define NETLIST_REGIONID_NVPERF_SYS_CONTROL 52 #define NETLIST_REGIONID_NVPERF_FBP_CONTROL 53 #define NETLIST_REGIONID_NVPERF_GPC_CONTROL 54 #define NETLIST_REGIONID_NVPERF_PMA_CONTROL 55 +#define NETLIST_REGIONID_CTXREG_LTS_BC 57 +#define NETLIST_REGIONID_CTXREG_LTS_UC 58 #endif struct netlist_region { @@ -107,6 +123,37 @@ struct netlist_gr_ucode { } gpccs, fecs; }; + +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +struct nvgpu_next_netlist_vars { + struct netlist_av_list sw_non_ctx_local_compute_load; + struct netlist_av_list sw_non_ctx_global_compute_load; +#ifdef CONFIG_NVGPU_GRAPHICS + struct netlist_av_list sw_non_ctx_local_gfx_load; + struct netlist_av_list sw_non_ctx_global_gfx_load; +#endif /* CONFIG_NVGPU_GRAPHICS */ +}; + +#ifdef CONFIG_NVGPU_DEBUGGER +struct nvgpu_next_ctxsw_regs { + struct netlist_aiv_list sys_compute; + struct netlist_aiv_list gpc_compute; + struct netlist_aiv_list tpc_compute; + struct netlist_aiv_list ppc_compute; + struct netlist_aiv_list etpc_compute; + struct netlist_aiv_list lts_bc; + struct netlist_aiv_list lts_uc; +#ifdef CONFIG_NVGPU_GRAPHICS + struct netlist_aiv_list sys_gfx; + struct netlist_aiv_list gpc_gfx; + struct netlist_aiv_list tpc_gfx; + struct netlist_aiv_list ppc_gfx; + struct netlist_aiv_list etpc_gfx; +#endif /* CONFIG_NVGPU_GRAPHICS */ +}; +#endif /* CONFIG_NVGPU_DEBUGGER */ + +#endif /* CONFIG_NVGPU_HAL_NON_FUSA */ struct nvgpu_netlist_vars { bool dynamic; diff --git a/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c b/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c deleted file mode 100644 index 534aabb21..000000000 --- a/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include "common/netlist/netlist_priv.h" - -/* Copied from common/netlist/netlist.c */ -static int nvgpu_netlist_alloc_load_av_list(struct gk20a *g, u8 *src, u32 len, - struct netlist_av_list *av_list) -{ - av_list->count = len / U32(sizeof(struct netlist_av)); - if (nvgpu_netlist_alloc_av_list(g, av_list) == NULL) { - return -ENOMEM; - } - - nvgpu_memcpy((u8 *)av_list->l, src, len); - - return 0; -} - -/* Copied from common/netlist/netlist.c */ -static int nvgpu_netlist_alloc_load_aiv_list(struct gk20a *g, u8 *src, u32 len, - struct netlist_aiv_list *aiv_list) -{ - aiv_list->count = len / U32(sizeof(struct netlist_aiv)); - if (nvgpu_netlist_alloc_aiv_list(g, aiv_list) == NULL) { - return -ENOMEM; - } - - nvgpu_memcpy((u8 *)aiv_list->l, src, len); - - return 0; -} - -#ifdef CONFIG_NVGPU_DEBUGGER -bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code) -{ - int err = 0; - bool handled = true; - - switch (region_id) { - case NETLIST_REGIONID_CTXREG_SYS_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.sys_compute); - break; - case NETLIST_REGIONID_CTXREG_GPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute); - break; - case NETLIST_REGIONID_CTXREG_TPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute); - break; - case NETLIST_REGIONID_CTXREG_PPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute); - break; - case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute); - break; - case NETLIST_REGIONID_CTXREG_LTS_BC: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.lts_bc); - break; - case NETLIST_REGIONID_CTXREG_LTS_UC: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.lts_uc); - break; - default: - handled = false; - break; - } - - if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) { - handled = true; - switch (region_id) { -#ifdef CONFIG_NVGPU_GRAPHICS - case NETLIST_REGIONID_CTXREG_SYS_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx); - break; - case NETLIST_REGIONID_CTXREG_GPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx); - break; - case NETLIST_REGIONID_CTXREG_TPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx); - break; - case NETLIST_REGIONID_CTXREG_PPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx); - break; - case NETLIST_REGIONID_CTXREG_ETPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx); - break; -#endif - default: - handled = false; - break; - } - } - *err_code = err; - - return handled; -} - -void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g) -{ - struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars; - - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l); -} -#endif /* CONFIG_NVGPU_DEBUGGER */ - -bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code) -{ - int err = 0; - bool handled = true; - - switch(region_id) { - case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load); - break; - case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load); - break; - default: - handled = false; - break; - } - - if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) { - handled = true; - switch (region_id) { -#ifdef CONFIG_NVGPU_GRAPHICS - case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load); - break; - case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load); - break; -#endif - default: - handled = false; - break; - } - } - *err_code = err; - - return handled; -} - -void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g) -{ - struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars; - - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l); - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l); -#ifdef CONFIG_NVGPU_GRAPHICS - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l); - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l); -#endif -} - -#ifdef CONFIG_NVGPU_DEBUGGER -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx; -} - -u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count); - return count; -} - -void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g) -{ - nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d", - nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", - nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", - nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d", - nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", - nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d", - nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count); -} -#endif /* CONFIG_NVGPU_DEBUGGER */ - -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list( - struct gk20a *g) -{ - return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load; -} - -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list( - struct gk20a *g) -{ - return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load; -} - -#ifdef CONFIG_NVGPU_GRAPHICS -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list( - struct gk20a *g) -{ - return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load; -} - -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list( - struct gk20a *g) -{ - return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load; -} -#endif /* CONFIG_NVGPU_GRAPHICS */ diff --git a/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h b/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h deleted file mode 100644 index cee5ae83f..000000000 --- a/drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_NETLIST_PRIV_H -#define NVGPU_NEXT_NETLIST_PRIV_H - -/** - * @file - * - * Declare netlist_vars specific struct and defines. - */ -#include - -struct gk20a; -struct netlist_av_list; -struct netlist_aiv_list; - -#ifdef CONFIG_NVGPU_DEBUGGER -#define NETLIST_REGIONID_CTXREG_SYS_COMPUTE 36 -#define NETLIST_REGIONID_CTXREG_GPC_COMPUTE 38 -#define NETLIST_REGIONID_CTXREG_TPC_COMPUTE 40 -#define NETLIST_REGIONID_CTXREG_PPC_COMPUTE 42 -#define NETLIST_REGIONID_CTXREG_ETPC_COMPUTE 44 -#ifdef CONFIG_NVGPU_GRAPHICS -#define NETLIST_REGIONID_CTXREG_SYS_GFX 37 -#define NETLIST_REGIONID_CTXREG_GPC_GFX 39 -#define NETLIST_REGIONID_CTXREG_TPC_GFX 41 -#define NETLIST_REGIONID_CTXREG_PPC_GFX 43 -#define NETLIST_REGIONID_CTXREG_ETPC_GFX 45 -#endif /* CONFIG_NVGPU_GRAPHICS */ -#endif /* CONFIG_NVGPU_DEBUGGER */ - -#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD 48 -#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD 50 -#ifdef CONFIG_NVGPU_GRAPHICS -#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD 49 -#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD 51 -#endif /* CONFIG_NVGPU_GRAPHICS */ - -#ifdef CONFIG_NVGPU_DEBUGGER -#define NETLIST_REGIONID_CTXREG_LTS_BC 57 -#define NETLIST_REGIONID_CTXREG_LTS_UC 58 -#endif /* CONFIG_DEBUGGER */ - -struct nvgpu_next_netlist_vars { - struct netlist_av_list sw_non_ctx_local_compute_load; - struct netlist_av_list sw_non_ctx_global_compute_load; -#ifdef CONFIG_NVGPU_GRAPHICS - struct netlist_av_list sw_non_ctx_local_gfx_load; - struct netlist_av_list sw_non_ctx_global_gfx_load; -#endif /* CONFIG_NVGPU_GRAPHICS */ -}; - -#ifdef CONFIG_NVGPU_DEBUGGER -struct nvgpu_next_ctxsw_regs { - struct netlist_aiv_list sys_compute; - struct netlist_aiv_list gpc_compute; - struct netlist_aiv_list tpc_compute; - struct netlist_aiv_list ppc_compute; - struct netlist_aiv_list etpc_compute; - struct netlist_aiv_list lts_bc; - struct netlist_aiv_list lts_uc; -#ifdef CONFIG_NVGPU_GRAPHICS - struct netlist_aiv_list sys_gfx; - struct netlist_aiv_list gpc_gfx; - struct netlist_aiv_list tpc_gfx; - struct netlist_aiv_list ppc_gfx; - struct netlist_aiv_list etpc_gfx; -#endif /* CONFIG_NVGPU_GRAPHICS */ -}; -#endif /* CONFIG_NVGPU_DEBUGGER */ - -#endif /* NVGPU_NEXT_NETLIST_PRIV_H */ diff --git a/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c b/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c deleted file mode 100644 index 5b64ef4c0..000000000 --- a/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "nvgpu_next_profiler.h" - -void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g) -{ - if (g->ops.perf.reset_hs_streaming_credits != NULL) { - /* Reset high speed streaming credits to 0. */ - g->ops.perf.reset_hs_streaming_credits(g); - } - - if (g->ops.perf.enable_hs_streaming != NULL) { - /* Disable high speed streaming */ - g->ops.perf.enable_hs_streaming(g, false); - } -} diff --git a/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h b/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h deleted file mode 100644 index 68e2ae33d..000000000 --- a/drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_PROFILER_H -#define NVGPU_NEXT_PROFILER_H - -void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g); - -#endif /* NVGPU_NEXT_PROFILER_H */ diff --git a/drivers/gpu/nvgpu/common/profiler/profiler.c b/drivers/gpu/nvgpu/common/profiler/profiler.c index 376f0be09..6bbc848bc 100644 --- a/drivers/gpu/nvgpu/common/profiler/profiler.c +++ b/drivers/gpu/nvgpu/common/profiler/profiler.c @@ -1157,3 +1157,18 @@ bool nvgpu_profiler_validate_regops_allowlist(struct nvgpu_profiler_object *prof offset = offset & (stride - 1U); return allowlist_offset_search(g, offset_allowlist, count, offset); } + +#ifdef CONFIG_NVGPU_HAL_NON_FUSA +void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g) +{ + if (g->ops.perf.reset_hs_streaming_credits != NULL) { + /* Reset high speed streaming credits to 0. */ + g->ops.perf.reset_hs_streaming_credits(g); + } + + if (g->ops.perf.enable_hs_streaming != NULL) { + /* Disable high speed streaming */ + g->ops.perf.enable_hs_streaming(g, false); + } +} +#endif /* CONFIG_NVGPU_HAL_NON_FUSA */ diff --git a/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c b/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c deleted file mode 100644 index ef07a70d1..000000000 --- a/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -static void nvgpu_next_sim_esc_readl(struct gk20a *g, - const char *path, u32 index, u32 *data) -{ - int err; - u32 data_offset; - - sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), - sim_escape_read_hdr_size()); - *sim_msg_param(g, 0) = index; - *sim_msg_param(g, 4) = sizeof(u32); - data_offset = round_up( - nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32)); - *sim_msg_param(g, 8) = data_offset; - strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path); - - err = issue_rpc_and_wait(g); - - if (err == 0) { - nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g, - nvgpu_safe_add_u32(data_offset, - sim_escape_read_hdr_size())), - sizeof(u32)); - } else { - *data = 0xffffffff; - WARN(1, "issue_rpc_and_wait failed err=%d", err); - } -} - -void nvgpu_next_init_sim_support(struct gk20a *g) -{ - if (g->sim) { - g->sim->esc_readl = nvgpu_next_sim_esc_readl; - } -} diff --git a/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c b/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c deleted file mode 100644 index 185d47f3f..000000000 --- a/drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "nvgpu/nvgpu_next_sim.h" - -int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g) -{ - u32 i; - struct netlist_av_list *sw_non_ctx_local_compute_load; - struct netlist_av_list *sw_non_ctx_local_gfx_load; - struct netlist_av_list *sw_non_ctx_global_compute_load; - struct netlist_av_list *sw_non_ctx_global_gfx_load; - - sw_non_ctx_local_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0, - &sw_non_ctx_local_compute_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_local_compute_load failed"); - } - - for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) { - struct netlist_av *l = sw_non_ctx_local_compute_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE", - i, &l[i].value); - } - -#ifdef CONFIG_NVGPU_GRAPHICS - sw_non_ctx_local_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0, - &sw_non_ctx_local_gfx_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_local_gfx_load failed"); - } - - for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) { - struct netlist_av *l = sw_non_ctx_local_gfx_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE", - i, &l[i].value); - } -#endif - - - sw_non_ctx_global_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0, - &sw_non_ctx_global_compute_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_global_compute_load failed"); - } - - for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) { - struct netlist_av *l = sw_non_ctx_global_compute_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE", - i, &l[i].value); - } - -#ifdef CONFIG_NVGPU_GRAPHICS - sw_non_ctx_global_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0, - &sw_non_ctx_global_gfx_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_global_gfx_load failed"); - } - - for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) { - struct netlist_av *l = sw_non_ctx_global_gfx_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE", - i, &l[i].value); - } -#endif - return 0; -} - -void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g) -{ - struct netlist_av_list *sw_non_ctx_local_compute_load; - struct netlist_av_list *sw_non_ctx_local_gfx_load; - struct netlist_av_list *sw_non_ctx_global_compute_load; - struct netlist_av_list *sw_non_ctx_global_gfx_load; - - sw_non_ctx_local_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); - sw_non_ctx_global_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); - - - nvgpu_kfree(g, sw_non_ctx_local_compute_load->l); - nvgpu_kfree(g, sw_non_ctx_global_compute_load->l); - -#ifdef CONFIG_NVGPU_GRAPHICS - sw_non_ctx_local_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); - sw_non_ctx_global_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); - - nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l); - nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l); -#endif -} - -#ifdef CONFIG_NVGPU_DEBUGGER -int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g) -{ - u32 i; - struct netlist_aiv_list *sys_compute_ctxsw_regs; - struct netlist_aiv_list *gpc_compute_ctxsw_regs; - struct netlist_aiv_list *tpc_compute_ctxsw_regs; - struct netlist_aiv_list *ppc_compute_ctxsw_regs; - struct netlist_aiv_list *etpc_compute_ctxsw_regs; - struct netlist_aiv_list *lts_ctxsw_regs; - struct netlist_aiv_list *sys_gfx_ctxsw_regs; - struct netlist_aiv_list *gpc_gfx_ctxsw_regs; - struct netlist_aiv_list *tpc_gfx_ctxsw_regs; - struct netlist_aiv_list *ppc_gfx_ctxsw_regs; - struct netlist_aiv_list *etpc_gfx_ctxsw_regs; - - sys_compute_ctxsw_regs = - nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0, - &sys_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "sys_compute_ctxsw_regs failed"); - } - - for (i = 0; i < sys_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = sys_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE", - i, &l[i].value); - } - - gpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0, - &gpc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "gpc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = gpc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE", - i, &l[i].value); - } - - tpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0, - &tpc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "tpc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = tpc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE", - i, &l[i].value); - } - - ppc_compute_ctxsw_regs = - nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0, - &ppc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "ppc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = ppc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE", - i, &l[i].value); - } - - etpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0, - &etpc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "etpc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = etpc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE", - i, &l[i].value); - } - - /* - * TODO: https://jirasw.nvidia.com/browse/NVGPU-5761 - */ - lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0, - <s_ctxsw_regs->count); - nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) { - nvgpu_info(g, "lts_ctxsw_regs failed"); - } - - for (i = 0U; i < lts_ctxsw_regs->count; i++) { - struct netlist_aiv *l = lts_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE", - i, &l[i].value); - nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr, - l[i].index, l[i].value); - } - - sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0, - &sys_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "sys_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = sys_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE", - i, &l[i].value); - } - - gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0, - &gpc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "gpc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0, - &tpc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "tpc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0, - &ppc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "ppc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0, - &etpc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "etpc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - return 0; -} - -void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g) -{ - struct netlist_aiv_list *sys_compute_ctxsw_regs; - struct netlist_aiv_list *gpc_compute_ctxsw_regs; - struct netlist_aiv_list *tpc_compute_ctxsw_regs; - struct netlist_aiv_list *ppc_compute_ctxsw_regs; - struct netlist_aiv_list *etpc_compute_ctxsw_regs; - struct netlist_aiv_list *lts_ctxsw_regs; - struct netlist_aiv_list *sys_gfx_ctxsw_regs; - struct netlist_aiv_list *gpc_gfx_ctxsw_regs; - struct netlist_aiv_list *tpc_gfx_ctxsw_regs; - struct netlist_aiv_list *ppc_gfx_ctxsw_regs; - struct netlist_aiv_list *etpc_gfx_ctxsw_regs; - - sys_compute_ctxsw_regs = - nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); - gpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); - tpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); - ppc_compute_ctxsw_regs = - nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); - etpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); - lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g); - - nvgpu_kfree(g, sys_compute_ctxsw_regs->l); - nvgpu_kfree(g, gpc_compute_ctxsw_regs->l); - nvgpu_kfree(g, tpc_compute_ctxsw_regs->l); - nvgpu_kfree(g, ppc_compute_ctxsw_regs->l); - nvgpu_kfree(g, etpc_compute_ctxsw_regs->l); - nvgpu_kfree(g, lts_ctxsw_regs->l); - - sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); - gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); - tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); - ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); - etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); - - nvgpu_kfree(g, sys_gfx_ctxsw_regs->l); - nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l); - nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l); - nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l); - nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l); -} -#endif /* CONFIG_NVGPU_DEBUGGER */ diff --git a/drivers/gpu/nvgpu/common/sim/sim.c b/drivers/gpu/nvgpu/common/sim/sim.c index 34e9b5d20..cff8871a9 100644 --- a/drivers/gpu/nvgpu/common/sim/sim.c +++ b/drivers/gpu/nvgpu/common/sim/sim.c @@ -301,3 +301,40 @@ int nvgpu_init_sim_support(struct gk20a *g) g->sim->esc_readl = nvgpu_sim_esc_readl; return 0; } + +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +static void nvgpu_next_sim_esc_readl(struct gk20a *g, + const char *path, u32 index, u32 *data) +{ + int err; + u32 data_offset; + + sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), + sim_escape_read_hdr_size()); + *sim_msg_param(g, 0) = index; + *sim_msg_param(g, 4) = sizeof(u32); + data_offset = round_up( + nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32)); + *sim_msg_param(g, 8) = data_offset; + strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path); + + err = issue_rpc_and_wait(g); + + if (err == 0) { + nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g, + nvgpu_safe_add_u32(data_offset, + sim_escape_read_hdr_size())), + sizeof(u32)); + } else { + *data = 0xffffffff; + WARN(1, "issue_rpc_and_wait failed err=%d", err); + } +} + +void nvgpu_next_init_sim_support(struct gk20a *g) +{ + if (g->sim) { + g->sim->esc_readl = nvgpu_next_sim_esc_readl; + } +} +#endif diff --git a/drivers/gpu/nvgpu/common/sim/sim_netlist.c b/drivers/gpu/nvgpu/common/sim/sim_netlist.c index ec87100ee..7b86d6022 100644 --- a/drivers/gpu/nvgpu/common/sim/sim_netlist.c +++ b/drivers/gpu/nvgpu/common/sim/sim_netlist.c @@ -24,9 +24,6 @@ #include #include #include -#if defined(CONFIG_NVGPU_NON_FUSA) -#include "nvgpu/nvgpu_next_sim.h" -#endif int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) { @@ -818,3 +815,424 @@ fail: return err; } + +#if defined(CONFIG_NVGPU_NON_FUSA) +int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g) +{ + u32 i; + struct netlist_av_list *sw_non_ctx_local_compute_load; + struct netlist_av_list *sw_non_ctx_local_gfx_load; + struct netlist_av_list *sw_non_ctx_global_compute_load; + struct netlist_av_list *sw_non_ctx_global_gfx_load; + + sw_non_ctx_local_compute_load = + nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0, + &sw_non_ctx_local_compute_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_local_compute_load failed"); + } + + for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) { + struct netlist_av *l = sw_non_ctx_local_compute_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE", + i, &l[i].value); + } + +#ifdef CONFIG_NVGPU_GRAPHICS + sw_non_ctx_local_gfx_load = + nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0, + &sw_non_ctx_local_gfx_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_local_gfx_load failed"); + } + + for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) { + struct netlist_av *l = sw_non_ctx_local_gfx_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE", + i, &l[i].value); + } +#endif + + + sw_non_ctx_global_compute_load = + nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0, + &sw_non_ctx_global_compute_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_global_compute_load failed"); + } + + for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) { + struct netlist_av *l = sw_non_ctx_global_compute_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE", + i, &l[i].value); + } + +#ifdef CONFIG_NVGPU_GRAPHICS + sw_non_ctx_global_gfx_load = + nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0, + &sw_non_ctx_global_gfx_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_global_gfx_load failed"); + } + + for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) { + struct netlist_av *l = sw_non_ctx_global_gfx_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE", + i, &l[i].value); + } +#endif + return 0; +} + +void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g) +{ + struct netlist_av_list *sw_non_ctx_local_compute_load; + struct netlist_av_list *sw_non_ctx_local_gfx_load; + struct netlist_av_list *sw_non_ctx_global_compute_load; + struct netlist_av_list *sw_non_ctx_global_gfx_load; + + sw_non_ctx_local_compute_load = + nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); + sw_non_ctx_global_compute_load = + nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); + + + nvgpu_kfree(g, sw_non_ctx_local_compute_load->l); + nvgpu_kfree(g, sw_non_ctx_global_compute_load->l); + +#ifdef CONFIG_NVGPU_GRAPHICS + sw_non_ctx_local_gfx_load = + nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); + sw_non_ctx_global_gfx_load = + nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); + + nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l); + nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l); +#endif +} + +#ifdef CONFIG_NVGPU_DEBUGGER +int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g) +{ + u32 i; + struct netlist_aiv_list *sys_compute_ctxsw_regs; + struct netlist_aiv_list *gpc_compute_ctxsw_regs; + struct netlist_aiv_list *tpc_compute_ctxsw_regs; + struct netlist_aiv_list *ppc_compute_ctxsw_regs; + struct netlist_aiv_list *etpc_compute_ctxsw_regs; + struct netlist_aiv_list *lts_ctxsw_regs; + struct netlist_aiv_list *sys_gfx_ctxsw_regs; + struct netlist_aiv_list *gpc_gfx_ctxsw_regs; + struct netlist_aiv_list *tpc_gfx_ctxsw_regs; + struct netlist_aiv_list *ppc_gfx_ctxsw_regs; + struct netlist_aiv_list *etpc_gfx_ctxsw_regs; + + sys_compute_ctxsw_regs = + nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0, + &sys_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "sys_compute_ctxsw_regs failed"); + } + + for (i = 0; i < sys_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = sys_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE", + i, &l[i].value); + } + + gpc_compute_ctxsw_regs = + nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0, + &gpc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "gpc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = gpc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE", + i, &l[i].value); + } + + tpc_compute_ctxsw_regs = + nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0, + &tpc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "tpc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = tpc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE", + i, &l[i].value); + } + + ppc_compute_ctxsw_regs = + nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0, + &ppc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "ppc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = ppc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE", + i, &l[i].value); + } + + etpc_compute_ctxsw_regs = + nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0, + &etpc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "etpc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = etpc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE", + i, &l[i].value); + } + + /* + * TODO: https://jirasw.nvidia.com/browse/NVGPU-5761 + */ + lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0, + <s_ctxsw_regs->count); + nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) { + nvgpu_info(g, "lts_ctxsw_regs failed"); + } + + for (i = 0U; i < lts_ctxsw_regs->count; i++) { + struct netlist_aiv *l = lts_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE", + i, &l[i].value); + nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr, + l[i].index, l[i].value); + } + + sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0, + &sys_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "sys_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = sys_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE", + i, &l[i].value); + } + + gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0, + &gpc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "gpc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE", + i, &l[i].value); + } + + tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0, + &tpc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "tpc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE", + i, &l[i].value); + } + + ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0, + &ppc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "ppc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE", + i, &l[i].value); + } + + etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0, + &etpc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "etpc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE", + i, &l[i].value); + } + + return 0; +} + +void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g) +{ + struct netlist_aiv_list *sys_compute_ctxsw_regs; + struct netlist_aiv_list *gpc_compute_ctxsw_regs; + struct netlist_aiv_list *tpc_compute_ctxsw_regs; + struct netlist_aiv_list *ppc_compute_ctxsw_regs; + struct netlist_aiv_list *etpc_compute_ctxsw_regs; + struct netlist_aiv_list *lts_ctxsw_regs; + struct netlist_aiv_list *sys_gfx_ctxsw_regs; + struct netlist_aiv_list *gpc_gfx_ctxsw_regs; + struct netlist_aiv_list *tpc_gfx_ctxsw_regs; + struct netlist_aiv_list *ppc_gfx_ctxsw_regs; + struct netlist_aiv_list *etpc_gfx_ctxsw_regs; + + sys_compute_ctxsw_regs = + nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); + gpc_compute_ctxsw_regs = + nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); + tpc_compute_ctxsw_regs = + nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); + ppc_compute_ctxsw_regs = + nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); + etpc_compute_ctxsw_regs = + nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); + lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g); + + nvgpu_kfree(g, sys_compute_ctxsw_regs->l); + nvgpu_kfree(g, gpc_compute_ctxsw_regs->l); + nvgpu_kfree(g, tpc_compute_ctxsw_regs->l); + nvgpu_kfree(g, ppc_compute_ctxsw_regs->l); + nvgpu_kfree(g, etpc_compute_ctxsw_regs->l); + nvgpu_kfree(g, lts_ctxsw_regs->l); + + sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); + gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); + tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); + ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); + etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); + + nvgpu_kfree(g, sys_gfx_ctxsw_regs->l); + nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l); + nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l); + nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l); + nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l); +} +#endif /* CONFIG_NVGPU_DEBUGGER */ +#endif diff --git a/drivers/gpu/nvgpu/hal/class/class_ga100.c b/drivers/gpu/nvgpu/hal/class/class_ga100.c index 0eb9dac7a..e6100dd74 100644 --- a/drivers/gpu/nvgpu/hal/class/class_ga100.c +++ b/drivers/gpu/nvgpu/hal/class/class_ga100.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021 NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,7 +21,6 @@ */ #include -#include #include #include "hal/class/class_ga10b.h" diff --git a/drivers/gpu/nvgpu/hal/class/class_ga10b.c b/drivers/gpu/nvgpu/hal/class/class_ga10b.c index ccfc12bd3..1d30bf5d4 100644 --- a/drivers/gpu/nvgpu/hal/class/class_ga10b.c +++ b/drivers/gpu/nvgpu/hal/class/class_ga10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021 NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,7 +21,6 @@ */ #include -#include #include #include "hal/class/class_tu104.h" diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c index be2d856cf..06d07313e 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c @@ -46,7 +46,6 @@ #include #include #include -#include #include "gr_ga10b.h" #include "hal/gr/gr/gr_gk20a.h" diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c index 860a6264c..535707152 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c index 42b5f50d4..8e2572dee 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c b/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c index 1a95d6138..fc2b8a070 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c @@ -22,7 +22,6 @@ #include #include -#include #include diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c index d24bc7c79..c2303fcd5 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c @@ -22,8 +22,6 @@ #include #include -#include -#include #include diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c index 5bd1cb0cb..97aa77c1f 100644 --- a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c +++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c @@ -31,7 +31,6 @@ #include #include #include -#include #include "hal/power_features/cg/gating_reglist.h" #include "ga100_gating_reglist.h" diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c index 0c471f2f0..70b9f6c5e 100644 --- a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c @@ -31,7 +31,6 @@ #include #include #include -#include #include "hal/power_features/cg/gating_reglist.h" #include "ga10b_gating_reglist.h" diff --git a/drivers/gpu/nvgpu/include/nvgpu/cic.h b/drivers/gpu/nvgpu/include/nvgpu/cic.h index fc5bbba73..74f1fdc07 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/cic.h +++ b/drivers/gpu/nvgpu/include/nvgpu/cic.h @@ -23,10 +23,72 @@ #ifndef NVGPU_CIC_H #define NVGPU_CIC_H +#include +#include #include #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_cic.h" +#define U32_BITS 32U +#define DIV_BY_U32_BITS(x) ((x) / U32_BITS) +#define MOD_BY_U32_BITS(x) ((x) % U32_BITS) + +#define RESET_ID_TO_REG_IDX(x) DIV_BY_U32_BITS((x)) +#define RESET_ID_TO_REG_BIT(x) MOD_BY_U32_BITS((x)) +#define RESET_ID_TO_REG_MASK(x) BIT32(RESET_ID_TO_REG_BIT((x))) + +#define GPU_VECTOR_TO_LEAF_REG(i) DIV_BY_U32_BITS((i)) +#define GPU_VECTOR_TO_LEAF_BIT(i) MOD_BY_U32_BITS((i)) +#define GPU_VECTOR_TO_LEAF_MASK(i) (BIT32(GPU_VECTOR_TO_LEAF_BIT(i))) +#define GPU_VECTOR_TO_SUBTREE(i) ((GPU_VECTOR_TO_LEAF_REG(i)) / 2U) +#define GPU_VECTOR_TO_LEAF_SHIFT(i) \ + (nvgpu_safe_mult_u32(((GPU_VECTOR_TO_LEAF_REG(i)) % 2U), 32U)) + +#define HOST2SOC_0_SUBTREE 0U +#define HOST2SOC_1_SUBTREE 1U +#define HOST2SOC_2_SUBTREE 2U +#define HOST2SOC_3_SUBTREE 3U +#define HOST2SOC_NUM_SUBTREE 4U + +#define HOST2SOC_SUBTREE_TO_TOP_IDX(i) ((i) / 32U) +#define HOST2SOC_SUBTREE_TO_TOP_BIT(i) ((i) % 32U) +#define HOST2SOC_SUBTREE_TO_LEAF0(i) \ + (nvgpu_safe_mult_u32((i), 2U)) +#define HOST2SOC_SUBTREE_TO_LEAF1(i) \ + (nvgpu_safe_add_u32((nvgpu_safe_mult_u32((i), 2U)), 1U)) + +#define STALL_SUBTREE_TOP_IDX 0U +#define STALL_SUBTREE_TOP_BITS \ + ((BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_1_SUBTREE))) | \ + (BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_2_SUBTREE))) | \ + (BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_3_SUBTREE)))) + +/** + * These should not contradict NVGPU_CIC_INTR_UNIT_* defines. + */ +#define NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR 10U +#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR 11U +#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR 12U +#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT 13U +#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT 14U +#define NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT 15U +#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0 16U +#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1 17U +#define NVGPU_CIC_INTR_UNIT_GR_STALL 18U +#define NVGPU_CIC_INTR_UNIT_CE_STALL 19U +#define NVGPU_CIC_INTR_UNIT_MAX 20U + +#define NVGPU_CIC_INTR_VECTORID_SIZE_MAX 32U +#define NVGPU_CIC_INTR_VECTORID_SIZE_ONE 1U + +#define RUNLIST_INTR_TREE_0 0U +#define RUNLIST_INTR_TREE_1 1U + +void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid, + u32 num_entries); +bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit); +bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree, + u64 *subtree_mask); + #endif struct nvgpu_err_desc; diff --git a/drivers/gpu/nvgpu/include/nvgpu/class.h b/drivers/gpu/nvgpu/include/nvgpu/class.h index 19f204e3e..e389179d7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/class.h +++ b/drivers/gpu/nvgpu/include/nvgpu/class.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -103,6 +103,16 @@ #define TURING_CHANNEL_GPFIFO_A 0xC46FU #define TURING_COMPUTE_A 0xC5C0U #define TURING_DMA_COPY_A 0xC5B5U + +#define AMPERE_SMC_PARTITION_REF 0xC637U +#define AMPERE_B 0xC797U +#define AMPERE_A 0xC697U +#define AMPERE_DMA_COPY_A 0xC6B5U +#define AMPERE_DMA_COPY_B 0xC7B5U +#define AMPERE_COMPUTE_A 0xC6C0U +#define AMPERE_COMPUTE_B 0xC7C0U +#define AMPERE_CHANNEL_GPFIFO_A 0xC56FU +#define AMPERE_CHANNEL_GPFIFO_B 0xC76FU #endif #endif /* NVGPU_CLASS_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/device.h b/drivers/gpu/nvgpu/include/nvgpu/device.h index b9de2cb03..d6c2d3dec 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/device.h +++ b/drivers/gpu/nvgpu/include/nvgpu/device.h @@ -31,10 +31,7 @@ #include #include - -#if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_device.h" -#endif +#include struct gk20a; @@ -93,6 +90,38 @@ struct gk20a; #define NVGPU_DEVICE_TOKEN_INIT 0U +#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) +struct nvgpu_device_next { + /** + * True if the device is an method engine behind host. + */ + bool engine; + + /** + * Runlist Engine ID; only valid if #engine is true. + */ + u32 rleng_id; + + /** + * Runlist PRI base - byte aligned based address. CHRAM offset can + * be computed from this. + */ + u32 rl_pri_base; + + /** + * PBDMA info for this device. It may contain multiple PBDMAs as + * there can now be multiple PBDMAs per runlist. + * + * This is in some ways awkward; devices seem to be more directly + * linked to runlists; runlists in turn have PBDMAs. Granted that + * means there's a computable relation between devices and PBDMAs + * it may make sense to not have this link. + */ + struct nvgpu_next_pbdma_info pbdma_info; + +}; +#endif + /** * Structure definition for storing information for the devices and the engines * available on the chip. diff --git a/drivers/gpu/nvgpu/include/nvgpu/ecc.h b/drivers/gpu/nvgpu/include/nvgpu/ecc.h index a5665f409..7d0d9279c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ecc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ecc.h @@ -173,7 +173,10 @@ struct nvgpu_ecc { /** SM icache uncorrected error count. */ struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count; #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/gr/nvgpu_next_gr_ecc.h" + /** SM RAMS corrected error count. */ + struct nvgpu_ecc_stat **sm_rams_ecc_corrected_err_count; + /** SM RAMS uncorrected error count. */ + struct nvgpu_ecc_stat **sm_rams_ecc_uncorrected_err_count; #endif /** GCC l1.5-cache corrected error count. */ @@ -226,7 +229,18 @@ struct nvgpu_ecc { /** hubmmu fillunit uncorrected error count. */ struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_err_count; #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_ecc.h" + /* Leave extra tab to fit into nvgpu_ecc.fb structure */ + struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_unique_err_count; + /** hubmmu l2tlb uncorrected unique error count. */ + struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_unique_err_count; + /** hubmmu hubtlb corrected unique error count. */ + struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_unique_err_count; + /** hubmmu hubtlb uncorrected unique error count. */ + struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_unique_err_count; + /** hubmmu fillunit corrected unique error count. */ + struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_unique_err_count; + /** hubmmu fillunit uncorrected unique error count. */ + struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_unique_err_count; #endif } fb; diff --git a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h index bfcb650d9..97ad7bb4b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h @@ -23,10 +23,6 @@ #ifndef NVGPU_ENGINE_STATUS_H #define NVGPU_ENGINE_STATUS_H -#if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_engine_status.h" -#endif - /** * @file * @@ -95,13 +91,20 @@ enum nvgpu_engine_status_ctx_status { NVGPU_CTX_STATUS_CTXSW_SWITCH, }; +#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) +struct nvgpu_next_engine_status_info { + /** Engine status_1 h/w register's read value. */ + u32 reg1_data; +}; +#endif + struct nvgpu_engine_status_info { /** Engine status h/w register's read value. */ u32 reg_data; #if defined(CONFIG_NVGPU_NON_FUSA) /** @cond DOXYGEN_SHOULD_SKIP_THIS */ - /* nvgpu next engine status additions */ - struct nvgpu_next_engine_status_info nvgpu_next; + /* Ampere+ engine status additions */ + struct nvgpu_next_engine_status_info nvgpu_next; /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #endif /** Channel or tsg id that is currently assigned to the engine. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index 2de405b62..a3ce8b289 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -30,9 +30,15 @@ #include +struct gk20a; +struct nvgpu_device; + /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_engines.h" +#define ENGINE_PBDMA_INSTANCE0 0U + +int nvgpu_next_engine_init_one_dev(struct gk20a *g, + const struct nvgpu_device *dev); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/errata.h b/drivers/gpu/nvgpu/include/nvgpu/errata.h index 5deb5426a..e1c41bf9d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/errata.h +++ b/drivers/gpu/nvgpu/include/nvgpu/errata.h @@ -35,7 +35,14 @@ struct gk20a; /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_errata.h" +#define ERRATA_FLAGS_NEXT \ + /* GA100 */ \ + DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"), \ + /* GA10B */ \ + DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"), \ + DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"), \ + DEFINE_ERRATA(NVGPU_ERRATA_3154076, "GA10B", "PROD VAL"), \ + DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"), #else #define ERRATA_FLAGS_NEXT #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/fb.h b/drivers/gpu/nvgpu/include/nvgpu/fb.h index 3e61ea4f7..e49d8348c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fb.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fb.h @@ -24,7 +24,44 @@ #define NVGPU_FB_H #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_fb.h" +/* VAB track all accesses (read and write) */ +#define NVGPU_VAB_MODE_ACCESS BIT32(0U) +/* VAB track only writes (writes and read-modify-writes) */ +#define NVGPU_VAB_MODE_DIRTY BIT32(1U) + +/* No change to VAB logging with VPR setting requested */ +#define NVGPU_VAB_LOGGING_VPR_NONE 0U +/* VAB logging disabled if vpr IN_USE=1, regardless of PROTECTED_MODE */ +#define NVGPU_VAB_LOGGING_VPR_IN_USE_DISABLED BIT32(0U) +/* VAB logging disabled if vpr PROTECTED_MODE=1, regardless of IN_USE */ +#define NVGPU_VAB_LOGGING_VPR_PROTECTED_DISABLED BIT32(1U) +/* VAB logging enabled regardless of IN_USE and PROTECTED_MODE */ +#define NVGPU_VAB_LOGGING_VPR_ENABLED BIT32(2U) +/* VAB logging disabled regardless of IN_USE and PROTECTED_MODE */ +#define NVGPU_VAB_LOGGING_VPR_DISABLED BIT32(3U) + +struct nvgpu_vab_range_checker { + + /* + * in: starting physical address. Must be aligned by + * 1 << (granularity_shift + bitmask_size_shift) where + * bitmask_size_shift is a HW specific constant. + */ + u64 start_phys_addr; + + /* in: log2 of coverage granularity per bit */ + u8 granularity_shift; + + u8 reserved[7]; +}; + +struct nvgpu_vab { + u32 user_num_range_checkers; + struct nvgpu_mem buffer; +}; + +int nvgpu_fb_vab_init_hal(struct gk20a *g); +int nvgpu_fb_vab_teardown_hal(struct gk20a *g); #endif /** diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h index 445e7598d..dc01dba1c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h @@ -33,7 +33,43 @@ struct gk20a; #include #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_fuse.h" +struct nvgpu_fuse_feature_override_ecc { + /** overide_ecc register feature */ + /** sm_lrf enable */ + bool sm_lrf_enable; + /** sm_lrf override */ + bool sm_lrf_override; + /** sm_l1_data enable */ + bool sm_l1_data_enable; + /** sm_l1_data overide */ + bool sm_l1_data_override; + /** sm_l1_tag enable */ + bool sm_l1_tag_enable; + /** sm_l1_tag overide */ + bool sm_l1_tag_override; + /** ltc enable */ + bool ltc_enable; + /** ltc overide */ + bool ltc_override; + /** dram enable */ + bool dram_enable; + /** dram overide */ + bool dram_override; + /** sm_cbu enable */ + bool sm_cbu_enable; + /** sm_cbu overide */ + bool sm_cbu_override; + + /** override_ecc_1 register feature */ + /** sm_l0_icache enable */ + bool sm_l0_icache_enable; + /** sm_l0_icache overide */ + bool sm_l0_icache_override; + /** sm_l1_icache enable */ + bool sm_l1_icache_enable; + /** sm_l1_icache overide */ + bool sm_l1_icache_override; +}; #endif #define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK BIT32(0) diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 2b5a9f05c..9b2e0e905 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -267,6 +267,11 @@ struct railgate_stats { #define GPU_LIT_MAX_RUNLISTS_SUPPORTED 49 #define GPU_LIT_NUM_LTC_LTS_SETS 50 #define GPU_LIT_NUM_LTC_LTS_WAYS 51 +#define GPU_LIT_ROP_IN_GPC_BASE 52 +#define GPU_LIT_ROP_IN_GPC_SHARED_BASE 53 +#define GPU_LIT_ROP_IN_GPC_PRI_SHARED_IDX 54 +#define GPU_LIT_ROP_IN_GPC_STRIDE 55 + /** @endcond */ /** Macro to get litter values corresponding to the litter defines. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h index b8d91512b..1951f4611 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h @@ -147,7 +147,7 @@ struct gops_ce { #endif #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_ce.h" + void (*intr_retrigger)(struct gk20a *g, u32 inst_id); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h b/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h index fa436b88d..dfc99d504 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/cg.h @@ -62,7 +62,20 @@ struct gops_cg { void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_hshub_load_gating_prod)(struct gk20a *g, bool prod); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_cg.h" + void (*slcg_runlist_load_gating_prod)(struct gk20a *g, bool prod); + void (*blcg_runlist_load_gating_prod)(struct gk20a *g, bool prod); + + /* Ring station slcg prod gops */ + void (*slcg_rs_ctrl_fbp_load_gating_prod)(struct gk20a *g, bool prod); + void (*slcg_rs_ctrl_gpc_load_gating_prod)(struct gk20a *g, bool prod); + void (*slcg_rs_ctrl_sys_load_gating_prod)(struct gk20a *g, bool prod); + void (*slcg_rs_fbp_load_gating_prod)(struct gk20a *g, bool prod); + void (*slcg_rs_gpc_load_gating_prod)(struct gk20a *g, bool prod); + void (*slcg_rs_sys_load_gating_prod)(struct gk20a *g, bool prod); + + void (*slcg_timer_load_gating_prod)(struct gk20a *g, bool prod); + + void (*elcg_ce_load_gating_prod)(struct gk20a *g, bool prod); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h index cff344811..e85566ddb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h @@ -103,7 +103,9 @@ struct gops_perf { int (*wait_for_idle_pmm_routers)(struct gk20a *g); int (*wait_for_idle_pma)(struct gk20a *g); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_perf.h" + void (*enable_hs_streaming)(struct gk20a *g, bool enable); + void (*reset_hs_streaming_credits)(struct gk20a *g); + void (*enable_pmasys_legacy_mode)(struct gk20a *g, bool enable); #endif }; struct gops_perfbuf { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h index 82fa1fbb5..49695a963 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fb.h @@ -162,7 +162,41 @@ struct gops_fb_ecc { }; #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_fb_vab.h" +struct nvgpu_vab_range_checker; + +struct gops_fb_vab { + /** + * @brief Initialize VAB + * + */ + int (*init)(struct gk20a *g); + + /** + * @brief Initialize VAB range checkers and enable VAB tracking + * + */ + int (*reserve)(struct gk20a *g, u32 vab_mode, u32 num_range_checkers, + struct nvgpu_vab_range_checker *vab_range_checker); + + /** + * @brief Trigger VAB dump, copy buffer to user and clear + * + */ + int (*dump_and_clear)(struct gk20a *g, u64 *user_buf, + u64 user_buf_size); + + /** + * @brief Disable VAB + * + */ + int (*release)(struct gk20a *g); + + /** + * @brief Free VAB resources + * + */ + int (*teardown)(struct gk20a *g); +}; #endif /** @@ -441,7 +475,14 @@ struct gops_fb { #endif #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_fb.h" + u32 (*get_num_active_ltcs)(struct gk20a *g); + +#ifdef CONFIG_NVGPU_MIG + int (*config_veid_smc_map)(struct gk20a *g, bool enable); + int (*set_smc_eng_config)(struct gk20a *g, bool enable); + int (*set_remote_swizid)(struct gk20a *g, bool enable); +#endif + struct gops_fb_vab vab; #endif #ifdef CONFIG_NVGPU_DGPU diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h index bba4653f2..d37832882 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h @@ -215,7 +215,7 @@ struct gops_fifo { #endif #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_fifo.h" + void (*runlist_intr_retrigger)(struct gk20a *g, u32 intr_tree); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h index f1297fd10..c9935d828 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h @@ -224,7 +224,12 @@ struct gops_fuse { #endif #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_fuse.h" + void (*write_feature_override_ecc)(struct gk20a *g, u32 val); + void (*write_feature_override_ecc_1)(struct gk20a *g, u32 val); + void (*read_feature_override_ecc)(struct gk20a *g, + struct nvgpu_fuse_feature_override_ecc *ecc_feature); + u32 (*fuse_opt_sm_ttu_en)(struct gk20a *g); + u32 (*opt_sec_source_isolation_en)(struct gk20a *g); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 7a05edc0a..80b06b2b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -454,7 +454,8 @@ struct gops_gr_intr { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_gr_intr.h" + void (*retrigger)(struct gk20a *g); + u32 (*enable_mask)(struct gk20a *g); #endif int (*handle_fecs_error)(struct gk20a *g, struct nvgpu_channel *ch, @@ -835,7 +836,11 @@ struct gops_gr_init { bool (*is_allowed_sw_bundle)(struct gk20a *g, u32 bundle_addr, u32 bundle_value, int *context); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_gr_init.h" + void (*auto_go_idle)(struct gk20a *g, bool enable); + void (*eng_config)(struct gk20a *g); + int (*reset_gpcs)(struct gk20a *g); + int (*sm_id_config_early)(struct gk20a *g, + struct nvgpu_gr_config *config); #endif /** @endcond */ }; @@ -967,7 +972,21 @@ struct gops_gr_ctxsw_prog { u32 aperture_mask); #endif #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h" +#ifdef CONFIG_NVGPU_DEBUGGER + u32 (*hw_get_main_header_size)(void); + u32 (*hw_get_gpccs_header_stride)(void); + u32 (*get_compute_sysreglist_offset)(u32 *fecs_hdr); + u32 (*get_gfx_sysreglist_offset)(u32 *fecs_hdr); + u32 (*get_ltsreglist_offset)(u32 *fecs_hdr); + u32 (*get_compute_gpcreglist_offset)(u32 *gpccs_hdr); + u32 (*get_gfx_gpcreglist_offset)(u32 *gpccs_hdr); + u32 (*get_compute_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num); + u32 (*get_gfx_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num); + u32 (*get_compute_ppcreglist_offset)(u32 *gpccs_hdr); + u32 (*get_gfx_ppcreglist_offset)(u32 *gpccs_hdr); + u32 (*get_compute_etpcreglist_offset)(u32 *gpccs_hdr); + u32 (*get_gfx_etpcreglist_offset)(u32 *gpccs_hdr); +#endif #endif }; /** @endcond */ @@ -1283,7 +1302,8 @@ struct gops_gr { struct gops_gr_zcull zcull; #endif /* CONFIG_NVGPU_GRAPHICS */ #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_gr.h" + void (*vab_init)(struct gk20a *g, u32 vab_reg); + void (*vab_release)(struct gk20a *g, u32 vab_reg); #endif /** @endcond */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h index d0deddd0f..aa74ba7bf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h @@ -77,8 +77,16 @@ struct gops_grmgr { void (*get_gpcgrp_count)(struct gk20a *g); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG) -#include "include/nvgpu/nvgpu_next_gops_grmgr.h" + u32 (*get_max_sys_pipes)(struct gk20a *g); + const struct nvgpu_mig_gpu_instance_config* (*get_mig_config_ptr)( + struct gk20a *g); + u32 (*get_allowed_swizzid_size)(struct gk20a *g); + int (*get_gpc_instance_gpcgrp_id)(struct gk20a *g, + u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id); + int (*get_mig_gpu_instance_config)(struct gk20a *g, + const char **config_name, u32 *num_config_supported); + void (*load_timestamp_prod)(struct gk20a *g); #endif }; -#endif /* NVGPU_NEXT_GOPS_GRMGR_H */ +#endif /* NVGPU_GOPS_GRMGR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h index 83a320354..52c4ceac8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h @@ -53,7 +53,8 @@ struct gops_ltc_intr { void (*configure)(struct gk20a *g); void (*en_illegal_compstat)(struct gk20a *g, bool enable); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_ltc_intr.h" + void (*isr_extra)(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value); + void (*ltc_intr3_configure_extra)(struct gk20a *g, u32 *reg); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; @@ -161,7 +162,8 @@ struct gops_ltc { int (*set_l2_sector_promotion)(struct gk20a *g, struct nvgpu_tsg *tsg, u32 policy); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_ltc.h" + u32 (*pri_shared_addr)(struct gk20a *g, u32 addr); + void (*ltc_lts_set_mgmt_setup)(struct gk20a *g); #endif #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h index 443c7a664..11a7cfffb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h @@ -259,7 +259,36 @@ struct gops_mc { #endif #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_mc.h" + /** + * @brief Reset HW engines. + * + * @param g [in] The GPU driver struct. + * @param devtype [in] Type of device. + * + * This function is invoked to reset the engines while initializing + * GR, CE and other engines during #nvgpu_finalize_poweron. + * + * Steps: + * - Compute reset mask for all engines of given devtype. + * - Disable given HW engines. + * - Acquire g->mc.enable_lock spinlock. + * - Read mc_device_enable_r register and clear the bits in read value + * corresponding to HW engines to be disabled. + * - Write mc_device_enable_r with the updated value. + * - Poll mc_device_enable_r to confirm register write success. + * - Release g->mc.enable_lock spinlock. + * - If GR engines are being reset, reset GPCs. + * - Enable the HW engines. + * - Acquire g->mc.enable_lock spinlock. + * - Read mc_device_enable_r register and set the bits in read value + * corresponding to HW engines to be enabled. + * - Write mc_device_enable_r with the updated value. + * - Poll mc_device_enable_r to confirm register write success. + * - Release g->mc.enable_lock spinlock. + */ + int (*reset_engines_all)(struct gk20a *g, u32 devtype); + void (*elpg_enable)(struct gk20a *g); + bool (*intr_get_unit_info)(struct gk20a *g, u32 unit); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h index 877024e25..0ca368be3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h @@ -90,7 +90,11 @@ struct gops_pbdma { void (*dump_status)(struct gk20a *g, struct nvgpu_debug_context *o); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_pbdma.h" + u32 (*set_channel_info_chid)(u32 chid); + u32 (*set_intr_notify)(u32 eng_intr_vector); + u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id); + void (*pbdma_force_ce_split)(struct gk20a *g); + u32 (*get_num_of_pbdmas)(void); #endif }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h index b47e6014f..dee0e38d4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h @@ -218,7 +218,7 @@ struct gops_pmu { * @param void * * @return Chip specific PMU Engine Falcon2 base address. - * For NEXT_GPUID, NEXT_GPUID PMU Engine Falcon2 base address + * For Ampere+, PMU Engine Falcon2 base address * will be returned. */ u32 (*falcon2_base_addr)(void); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h b/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h index d11e5a84f..58375b966 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h @@ -146,8 +146,10 @@ struct gops_priv_ring { #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ -#if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_priv_ring.h" +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG) + int (*config_gr_remap_window)(struct gk20a *g, u32 gr_syspipe_indx, + bool enable); + int (*config_gpc_rs_map)(struct gk20a *g, bool enable); #endif }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h index 2c065e9a5..95b892854 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h @@ -90,7 +90,15 @@ struct gops_runlist { void (*init_enginfo)(struct gk20a *g, struct nvgpu_fifo *f); u32 (*get_tsg_max_timeslice)(void); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_gops_runlist.h" + u32 (*get_runlist_id)(struct gk20a *g, u32 runlist_pri_base); + u32 (*get_engine_id_from_rleng_id)(struct gk20a *g, + u32 rleng_id, u32 runlist_pri_base); + u32 (*get_chram_bar0_offset)(struct gk20a *g, u32 runlist_pri_base); + void (*get_pbdma_info)(struct gk20a *g, u32 runlist_pri_base, + struct nvgpu_next_pbdma_info *pbdma_info); + u32 (*get_engine_intr_id)(struct gk20a *g, u32 runlist_pri_base, + u32 rleng_id); + u32 (*get_esched_fb_thread_id)(struct gk20a *g, u32 runlist_pri_base); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h index 761711966..591af661f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h @@ -53,7 +53,7 @@ struct nvgpu_gr_config; int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config); /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/gr/nvgpu_next_fs_state.h" +int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h index 64370292b..a24c499be 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h @@ -118,6 +118,7 @@ struct gk20a; struct nvgpu_gr; struct nvgpu_gr_config; +struct netlist_av_list; /** * @brief Allocate memory for GR struct and initialize the minimum SW @@ -353,7 +354,8 @@ int nvgpu_gr_reset(struct gk20a *g); /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/gr/nvgpu_next_gr.h" +void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g); +void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h deleted file mode 100644 index 94ee10a76..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_FS_STATE_H -#define NVGPU_NEXT_FS_STATE_H - -struct gk20a; -struct nvgpu_gr_config; - -int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config); - -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h deleted file mode 100644 index 636172302..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_GR_H -#define NVGPU_NEXT_GR_H - -/** - * @file - * - */ -#include - -struct gk20a; -struct netlist_av_list; - -void nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g); -void nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g); -#endif /* NVGPU_NEXT_GR_H */ \ No newline at end of file diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h b/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h deleted file mode 100644 index 73ab1d188..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GR_ECC_H -#define NVGPU_NEXT_GR_ECC_H - - /** SM RAMS corrected error count. */ - struct nvgpu_ecc_stat **sm_rams_ecc_corrected_err_count; - /** SM RAMS uncorrected error count. */ - struct nvgpu_ecc_stat **sm_rams_ecc_uncorrected_err_count; - -#endif /* NVGPU_NEXT_GR_ECC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h index 74bf9d5f6..47dc80538 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h @@ -117,14 +117,11 @@ #include #include #include +#include struct gk20a; struct nvgpu_device; -#if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_mc.h" -#endif - #define MC_ENABLE_DELAY_US 20U #define MC_RESET_DELAY_US 20U #define MC_RESET_CE_DELAY_US 500U @@ -163,6 +160,44 @@ struct nvgpu_device; /** Bit offset of the Architecture field in the HW version register */ #define NVGPU_GPU_ARCHITECTURE_SHIFT 4U +#if defined(CONFIG_NVGPU_NON_FUSA) +struct nvgpu_intr_unit_info { + /** + * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1 + * top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3 + * top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5 + * top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7 + */ + /** + * h/w defined vectorids for the s/w defined intr unit. + * Upto 32 vectorids (32 bits of a leaf register) are supported for + * the intr units that support multiple vector ids. + */ + u32 vectorid[NVGPU_CIC_INTR_VECTORID_SIZE_MAX]; + /** number of vectorid supported by the intr unit */ + u32 vectorid_size; + u32 subtree; /** subtree number corresponding to vectorid */ + u64 subtree_mask; /** leaf1_leaf0 value for the intr unit */ + /** + * This flag will be set to true after all the fields + * of nvgpu_intr_unit_info are configured. + */ + bool valid; +}; + +struct nvgpu_next_mc { + /** + * intr info array indexed by s/w defined intr unit name + */ + struct nvgpu_intr_unit_info intr_unit_info[NVGPU_CIC_INTR_UNIT_MAX]; + /** + * Leaf mask per subtree. Subtree is a pair of leaf registers. + * Each subtree corresponds to a bit in intr_top register. + */ + u64 subtree_mask_restore[HOST2SOC_NUM_SUBTREE]; +}; +#endif + /** * This struct holds the variables needed to manage the configuration and * interrupt handling of the units/engines. diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h index 4a7aaa899..7e8872a63 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h @@ -457,7 +457,8 @@ struct mm_gk20a { struct nvgpu_mem mmu_rd_mem; #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_mm.h" + /** VAB struct */ + struct nvgpu_vab vab; #endif }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/netlist.h b/drivers/gpu/nvgpu/include/nvgpu/netlist.h index 8804112c4..eeb5e9874 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/netlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/netlist.h @@ -29,6 +29,7 @@ #include struct gk20a; +struct nvgpu_netlist_vars; /** * Description of netlist Address-Value(av) structure. @@ -347,11 +348,6 @@ u32 *nvgpu_netlist_get_gpccs_inst_list(struct gk20a *g); */ u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g); -/** @cond DOXYGEN_SHOULD_SKIP_THIS */ -#if defined(CONFIG_NVGPU_NON_FUSA) -#include -#endif - #ifdef CONFIG_NVGPU_DEBUGGER struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g); struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g); @@ -410,6 +406,60 @@ struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g); void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set); void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size); void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index); + +bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g, + u32 region_id, u8 *src, u32 size, + struct nvgpu_netlist_vars *netlist_vars, int *err_code); +void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g); + +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list( + struct gk20a *g); +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list( + struct gk20a *g); +#ifdef CONFIG_NVGPU_GRAPHICS +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list( + struct gk20a *g); +struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list( + struct gk20a *g); +#endif /* CONFIG_NVGPU_GRAPHICS */ + +#ifdef CONFIG_NVGPU_DEBUGGER +bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g, + u32 region_id, u8 *src, u32 size, + struct nvgpu_netlist_vars *netlist_vars, int *err_code); +void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g); + +struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs( + struct gk20a *g); +#ifdef CONFIG_NVGPU_GRAPHICS +struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs( + struct gk20a *g); +struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs( + struct gk20a *g); +#endif /* CONFIG_NVGPU_GRAPHICS */ +u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g); +u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g); +u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g); +u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g); +u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g); +void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g); +#endif /* CONFIG_NVGPU_DEBUGGER */ #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h index 1cdfddda3..2d190048a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h @@ -101,6 +101,11 @@ struct mmu_fault_info; #define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED (17U) #define GPU_SM_MACHINE_CHECK_ERROR (18U) #define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED (20U) +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +#define GPU_SM_RAMS_ECC_CORRECTED (21U) +#define GPU_SM_RAMS_ECC_UNCORRECTED (22U) +#endif + /** * @} */ @@ -814,8 +819,4 @@ void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit, void gr_intr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid, u32 mailbox_value); -#if defined(CONFIG_NVGPU_HAL_NON_FUSA) -#include "include/nvgpu/nvgpu_next_err.h" -#endif - #endif /* NVGPU_NVGPU_ERR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h deleted file mode 100644 index d406b2e8f..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_CIC_H -#define NVGPU_NEXT_CIC_H - -/** - * @file - * - * Declare intr specific struct and defines. - */ -#include -#include - -#define U32_BITS 32U -#define DIV_BY_U32_BITS(x) ((x) / U32_BITS) -#define MOD_BY_U32_BITS(x) ((x) % U32_BITS) - -#define RESET_ID_TO_REG_IDX(x) DIV_BY_U32_BITS((x)) -#define RESET_ID_TO_REG_BIT(x) MOD_BY_U32_BITS((x)) -#define RESET_ID_TO_REG_MASK(x) BIT32(RESET_ID_TO_REG_BIT((x))) - -#define GPU_VECTOR_TO_LEAF_REG(i) DIV_BY_U32_BITS((i)) -#define GPU_VECTOR_TO_LEAF_BIT(i) MOD_BY_U32_BITS((i)) -#define GPU_VECTOR_TO_LEAF_MASK(i) (BIT32(GPU_VECTOR_TO_LEAF_BIT(i))) -#define GPU_VECTOR_TO_SUBTREE(i) ((GPU_VECTOR_TO_LEAF_REG(i)) / 2U) -#define GPU_VECTOR_TO_LEAF_SHIFT(i) \ - (nvgpu_safe_mult_u32(((GPU_VECTOR_TO_LEAF_REG(i)) % 2U), 32U)) - -#define HOST2SOC_0_SUBTREE 0U -#define HOST2SOC_1_SUBTREE 1U -#define HOST2SOC_2_SUBTREE 2U -#define HOST2SOC_3_SUBTREE 3U -#define HOST2SOC_NUM_SUBTREE 4U - -#define HOST2SOC_SUBTREE_TO_TOP_IDX(i) ((i) / 32U) -#define HOST2SOC_SUBTREE_TO_TOP_BIT(i) ((i) % 32U) -#define HOST2SOC_SUBTREE_TO_LEAF0(i) \ - (nvgpu_safe_mult_u32((i), 2U)) -#define HOST2SOC_SUBTREE_TO_LEAF1(i) \ - (nvgpu_safe_add_u32((nvgpu_safe_mult_u32((i), 2U)), 1U)) - -#define STALL_SUBTREE_TOP_IDX 0U -#define STALL_SUBTREE_TOP_BITS \ - ((BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_1_SUBTREE))) | \ - (BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_2_SUBTREE))) | \ - (BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_3_SUBTREE)))) - -/** - * These should not contradict NVGPU_CIC_INTR_UNIT_* defines. - */ -#define NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR 10U -#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR 11U -#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR 12U -#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT 13U -#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT 14U -#define NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT 15U -#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0 16U -#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1 17U -#define NVGPU_CIC_INTR_UNIT_GR_STALL 18U -#define NVGPU_CIC_INTR_UNIT_CE_STALL 19U -#define NVGPU_CIC_INTR_UNIT_MAX 20U - -#define NVGPU_CIC_INTR_VECTORID_SIZE_MAX 32U -#define NVGPU_CIC_INTR_VECTORID_SIZE_ONE 1U - -#define RUNLIST_INTR_TREE_0 0U -#define RUNLIST_INTR_TREE_1 1U - -void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid, - u32 num_entries); -bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit); -bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree, - u64 *subtree_mask); - -#endif /* NVGPU_NEXT_CIC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h deleted file mode 100644 index daefcd83a..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_CLASS_H -#define NVGPU_NEXT_CLASS_H - -#define AMPERE_SMC_PARTITION_REF 0xC637U -#define AMPERE_B 0xC797U -#define AMPERE_A 0xC697U -#define AMPERE_DMA_COPY_A 0xC6B5U -#define AMPERE_DMA_COPY_B 0xC7B5U -#define AMPERE_COMPUTE_A 0xC6C0U -#define AMPERE_COMPUTE_B 0xC7C0U -#define AMPERE_CHANNEL_GPFIFO_A 0xC56FU -#define AMPERE_CHANNEL_GPFIFO_B 0xC76FU - -#endif /* NVGPU_NEXT_CLASS_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h deleted file mode 100644 index 98a450029..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_TOP_H -#define NVGPU_NEXT_TOP_H - -#include - -struct nvgpu_device_next { - /** - * True if the device is an method engine behind host. - */ - bool engine; - - /** - * Runlist Engine ID; only valid if #engine is true. - */ - u32 rleng_id; - - /** - * Runlist PRI base - byte aligned based address. CHRAM offset can - * be computed from this. - */ - u32 rl_pri_base; - - /** - * PBDMA info for this device. It may contain multiple PBDMAs as - * there can now be multiple PBDMAs per runlist. - * - * This is in some ways awkward; devices seem to be more directly - * linked to runlists; runlists in turn have PBDMAs. Granted that - * means there's a computable relation between devices and PBDMAs - * it may make sense to not have this link. - */ - struct nvgpu_next_pbdma_info pbdma_info; - -}; - -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h deleted file mode 100644 index 3ddb016a7..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_ECC_H -#define NVGPU_NEXT_ECC_H - - /* Leave extra tab to fit into nvgpu_ecc.fb structure */ - struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_unique_err_count; - /** hubmmu l2tlb uncorrected unique error count. */ - struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_unique_err_count; - /** hubmmu hubtlb corrected unique error count. */ - struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_unique_err_count; - /** hubmmu hubtlb uncorrected unique error count. */ - struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_unique_err_count; - /** hubmmu fillunit corrected unique error count. */ - struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_unique_err_count; - /** hubmmu fillunit uncorrected unique error count. */ - struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_unique_err_count; - -#endif /* NVGPU_NEXT_ECC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h deleted file mode 100644 index deb981dcf..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_ENGINE_STATUS_H -#define NVGPU_NEXT_ENGINE_STATUS_H - -/** - * @file - * - * Declare device info specific struct and defines. - */ -#include - -struct nvgpu_next_engine_status_info { - /** Engine status_1 h/w register's read value. */ - u32 reg1_data; -}; -#endif /* NVGPU_NEXT_ENGINE_STATUS_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h deleted file mode 100644 index 77754d5af..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_ENGINES_H -#define NVGPU_NEXT_ENGINES_H - -/** - * @file - * - * Declare engine info specific struct and defines. - */ -#include - -struct gk20a; -struct nvgpu_device; - -#define ENGINE_PBDMA_INSTANCE0 0U - -int nvgpu_next_engine_init_one_dev(struct gk20a *g, - const struct nvgpu_device *dev); - -#endif /* NVGPU_NEXT_ENGINES_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h deleted file mode 100644 index 0744909e2..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_ERR_H -#define NVGPU_NEXT_ERR_H - -/* - * Error IDs for SM unit. - */ -#define GPU_SM_RAMS_ECC_CORRECTED (21U) -#define GPU_SM_RAMS_ECC_UNCORRECTED (22U) - -#endif /* NVGPU_NEXT_ERR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h deleted file mode 100644 index 9628c37d3..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_ERRATA_H -#define NVGPU_NEXT_ERRATA_H - -#define ERRATA_FLAGS_NEXT \ - /* GA100 */ \ - DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"), \ - /* GA10B */ \ - DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"), \ - DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"), \ - DEFINE_ERRATA(NVGPU_ERRATA_3154076, "GA10B", "PROD VAL"), \ - DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"), - -#endif /* NVGPU_NEXT_ERRATA_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h deleted file mode 100644 index 6263e98fc..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_FB_H -#define NVGPU_NEXT_FB_H - -/* VAB track all accesses (read and write) */ -#define NVGPU_VAB_MODE_ACCESS BIT32(0U) -/* VAB track only writes (writes and read-modify-writes) */ -#define NVGPU_VAB_MODE_DIRTY BIT32(1U) - -/* No change to VAB logging with VPR setting requested */ -#define NVGPU_VAB_LOGGING_VPR_NONE 0U -/* VAB logging disabled if vpr IN_USE=1, regardless of PROTECTED_MODE */ -#define NVGPU_VAB_LOGGING_VPR_IN_USE_DISABLED BIT32(0U) -/* VAB logging disabled if vpr PROTECTED_MODE=1, regardless of IN_USE */ -#define NVGPU_VAB_LOGGING_VPR_PROTECTED_DISABLED BIT32(1U) -/* VAB logging enabled regardless of IN_USE and PROTECTED_MODE */ -#define NVGPU_VAB_LOGGING_VPR_ENABLED BIT32(2U) -/* VAB logging disabled regardless of IN_USE and PROTECTED_MODE */ -#define NVGPU_VAB_LOGGING_VPR_DISABLED BIT32(3U) - -struct nvgpu_vab_range_checker { - - /* - * in: starting physical address. Must be aligned by - * 1 << (granularity_shift + bitmask_size_shift) where - * bitmask_size_shift is a HW specific constant. - */ - u64 start_phys_addr; - - /* in: log2 of coverage granularity per bit */ - u8 granularity_shift; - - u8 reserved[7]; -}; - -struct nvgpu_vab { - u32 user_num_range_checkers; - struct nvgpu_mem buffer; -}; - -int nvgpu_fb_vab_init_hal(struct gk20a *g); -int nvgpu_fb_vab_teardown_hal(struct gk20a *g); - -#endif /* NVGPU_NEXT_FB_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h deleted file mode 100644 index 5e687ae53..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_FUSE_H -#define NVGPU_NEXT_FUSE_H - -/** - * @file - * - * Declare device info specific struct and defines. - */ -#include - -struct nvgpu_fuse_feature_override_ecc { - /** overide_ecc register feature */ - /** sm_lrf enable */ - bool sm_lrf_enable; - /** sm_lrf override */ - bool sm_lrf_override; - /** sm_l1_data enable */ - bool sm_l1_data_enable; - /** sm_l1_data overide */ - bool sm_l1_data_override; - /** sm_l1_tag enable */ - bool sm_l1_tag_enable; - /** sm_l1_tag overide */ - bool sm_l1_tag_override; - /** ltc enable */ - bool ltc_enable; - /** ltc overide */ - bool ltc_override; - /** dram enable */ - bool dram_enable; - /** dram overide */ - bool dram_override; - /** sm_cbu enable */ - bool sm_cbu_enable; - /** sm_cbu overide */ - bool sm_cbu_override; - - /** override_ecc_1 register feature */ - /** sm_l0_icache enable */ - bool sm_l0_icache_enable; - /** sm_l0_icache overide */ - bool sm_l0_icache_override; - /** sm_l1_icache enable */ - bool sm_l1_icache_enable; - /** sm_l1_icache overide */ - bool sm_l1_icache_override; -}; - -#endif /* NVGPU_NEXT_FUSE_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h deleted file mode 100644 index f6997b952..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_CE_H -#define NVGPU_NEXT_GOPS_CE_H - - /* Leave extra tab to fit into gops_ce structure */ - - void (*intr_retrigger)(struct gk20a *g, u32 inst_id); - -#endif /* NVGPU_NEXT_GOPS_CE_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h deleted file mode 100644 index 0dd821d58..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_CG_H -#define NVGPU_NEXT_GOPS_CG_H - - /* Leave extra tab to fit into gops_cg structure */ - - void (*slcg_runlist_load_gating_prod)(struct gk20a *g, bool prod); - void (*blcg_runlist_load_gating_prod)(struct gk20a *g, bool prod); - - /* Ring station slcg prod gops */ - void (*slcg_rs_ctrl_fbp_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_rs_ctrl_gpc_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_rs_ctrl_sys_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_rs_fbp_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_rs_gpc_load_gating_prod)(struct gk20a *g, bool prod); - void (*slcg_rs_sys_load_gating_prod)(struct gk20a *g, bool prod); - - void (*slcg_timer_load_gating_prod)(struct gk20a *g, bool prod); - - void (*elcg_ce_load_gating_prod)(struct gk20a *g, bool prod); - -#endif /* NVGPU_NEXT_GOPS_CG_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h deleted file mode 100644 index 57658ec0a..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_FB_H -#define NVGPU_NEXT_GOPS_FB_H - - /* Leave extra tab to fit into gops_fb structure */ - - u32 (*get_num_active_ltcs)(struct gk20a *g); - -#ifdef CONFIG_NVGPU_MIG - int (*config_veid_smc_map)(struct gk20a *g, bool enable); - int (*set_smc_eng_config)(struct gk20a *g, bool enable); - int (*set_remote_swizid)(struct gk20a *g, bool enable); -#endif - struct gops_fb_vab vab; - -#endif /* NVGPU_NEXT_GOPS_FB_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h deleted file mode 100644 index a215868cc..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_FB_VAB_H -#define NVGPU_NEXT_GOPS_FB_VAB_H - -struct nvgpu_vab_range_checker; - -struct gops_fb_vab { - /** - * @brief Initialize VAB - * - */ - int (*init)(struct gk20a *g); - - /** - * @brief Initialize VAB range checkers and enable VAB tracking - * - */ - int (*reserve)(struct gk20a *g, u32 vab_mode, u32 num_range_checkers, - struct nvgpu_vab_range_checker *vab_range_checker); - - /** - * @brief Trigger VAB dump, copy buffer to user and clear - * - */ - int (*dump_and_clear)(struct gk20a *g, u64 *user_buf, - u64 user_buf_size); - - /** - * @brief Disable VAB - * - */ - int (*release)(struct gk20a *g); - - /** - * @brief Free VAB resources - * - */ - int (*teardown)(struct gk20a *g); -}; - -#endif /* NVGPU_NEXT_GOPS_FB_VAB_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h deleted file mode 100644 index affe95b7f..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_FIFO_H -#define NVGPU_NEXT_GOPS_FIFO_H - - /* Leave extra tab to fit into gops_fifo structure */ - - void (*runlist_intr_retrigger)(struct gk20a *g, u32 intr_tree); - -#endif /* NVGPU_NEXT_GOPS_FIFO_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h deleted file mode 100644 index 1d6957511..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_FUSE_H -#define NVGPU_NEXT_GOPS_FUSE_H - - /* Leave extra tab to fit into gops_fuse structure */ - - void (*write_feature_override_ecc)(struct gk20a *g, u32 val); - void (*write_feature_override_ecc_1)(struct gk20a *g, u32 val); - void (*read_feature_override_ecc)(struct gk20a *g, - struct nvgpu_fuse_feature_override_ecc *ecc_feature); - u32 (*fuse_opt_sm_ttu_en)(struct gk20a *g); - u32 (*opt_sec_source_isolation_en)(struct gk20a *g); - -#endif /* NVGPU_NEXT_GOPS_FUSE_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h deleted file mode 100644 index d470f4bc3..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_GR_H -#define NVGPU_NEXT_GOPS_GR_H - - /* Leave extra tab to fit into gops_gr_intr structure */ - void (*vab_init)(struct gk20a *g, u32 vab_reg); - void (*vab_release)(struct gk20a *g, u32 vab_reg); - -#endif /* NVGPU_NEXT_GOPS_GR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h deleted file mode 100644 index 13fcab4c7..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_GR_CTXSW_PROG_H -#define NVGPU_NEXT_GOPS_GR_CTXSW_PROG_H - -#ifdef CONFIG_NVGPU_DEBUGGER - u32 (*hw_get_main_header_size)(void); - u32 (*hw_get_gpccs_header_stride)(void); - u32 (*get_compute_sysreglist_offset)(u32 *fecs_hdr); - u32 (*get_gfx_sysreglist_offset)(u32 *fecs_hdr); - u32 (*get_ltsreglist_offset)(u32 *fecs_hdr); - u32 (*get_compute_gpcreglist_offset)(u32 *gpccs_hdr); - u32 (*get_gfx_gpcreglist_offset)(u32 *gpccs_hdr); - u32 (*get_compute_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num); - u32 (*get_gfx_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num); - u32 (*get_compute_ppcreglist_offset)(u32 *gpccs_hdr); - u32 (*get_gfx_ppcreglist_offset)(u32 *gpccs_hdr); - u32 (*get_compute_etpcreglist_offset)(u32 *gpccs_hdr); - u32 (*get_gfx_etpcreglist_offset)(u32 *gpccs_hdr); -#endif - -#endif /* NVGPU_NEXT_GOPS_GR_CTXSW_PROG_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h deleted file mode 100644 index 91c67adc8..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_init.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_GR_INIT_H -#define NVGPU_NEXT_GOPS_GR_INIT_H - - /* Leave extra tab to fit into gops_gr structure */ - - void (*auto_go_idle)(struct gk20a *g, bool enable); - void (*eng_config)(struct gk20a *g); - int (*reset_gpcs)(struct gk20a *g); - int (*sm_id_config_early)(struct gk20a *g, - struct nvgpu_gr_config *config); - -#endif /* NVGPU_NEXT_GOPS_GR_INIT_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h deleted file mode 100644 index a3517ab71..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr_intr.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_GR_INTR_H -#define NVGPU_NEXT_GOPS_GR_INTR_H - - /* Leave extra tab to fit into gops_gr_intr structure */ - void (*retrigger)(struct gk20a *g); - u32 (*enable_mask)(struct gk20a *g); - -#endif /* NVGPU_NEXT_GOPS_GR_INTR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h deleted file mode 100644 index 189476636..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_grmgr.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_GRMGR_H -#define NVGPU_NEXT_GOPS_GRMGR_H - - /* Leave extra tab to fit into gops_grmgr structure */ - - u32 (*get_max_sys_pipes)(struct gk20a *g); - const struct nvgpu_mig_gpu_instance_config* (*get_mig_config_ptr)( - struct gk20a *g); - u32 (*get_allowed_swizzid_size)(struct gk20a *g); - int (*get_gpc_instance_gpcgrp_id)(struct gk20a *g, - u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id); - int (*get_mig_gpu_instance_config)(struct gk20a *g, - const char **config_name, u32 *num_config_supported); - void (*load_timestamp_prod)(struct gk20a *g); - -#endif /* NVGPU_NEXT_GOPS_GRMGR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h deleted file mode 100644 index 63ac81217..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_LTC_H -#define NVGPU_NEXT_GOPS_LTC_H - - /* Leave extra tab to fit into gops_ltc structure */ - u32 (*pri_shared_addr)(struct gk20a *g, u32 addr); - void (*ltc_lts_set_mgmt_setup)(struct gk20a *g); -#endif /* NVGPU_NEXT_GOPS_LTC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h deleted file mode 100644 index 6c78c8f4b..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ltc_intr.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_LTC_INTR_H -#define NVGPU_NEXT_GOPS_LTC_INTR_H - - /* Leave extra tab to fit into gops_ltc structure */ - void (*isr_extra)(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value); - void (*ltc_intr3_configure_extra)(struct gk20a *g, u32 *reg); - -#endif /* NVGPU_NEXT_GOPS_LTC_INTR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h deleted file mode 100644 index 4cf160516..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_mc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_MC_H -#define NVGPU_NEXT_GOPS_MC_H - - /* Leave extra tab to fit into gops_mc structure */ - - /** - * @brief Reset HW engines. - * - * @param g [in] The GPU driver struct. - * @param devtype [in] Type of device. - * - * This function is invoked to reset the engines while initializing - * GR, CE and other engines during #nvgpu_finalize_poweron. - * - * Steps: - * - Compute reset mask for all engines of given devtype. - * - Disable given HW engines. - * - Acquire g->mc.enable_lock spinlock. - * - Read mc_device_enable_r register and clear the bits in read value - * corresponding to HW engines to be disabled. - * - Write mc_device_enable_r with the updated value. - * - Poll mc_device_enable_r to confirm register write success. - * - Release g->mc.enable_lock spinlock. - * - If GR engines are being reset, reset GPCs. - * - Enable the HW engines. - * - Acquire g->mc.enable_lock spinlock. - * - Read mc_device_enable_r register and set the bits in read value - * corresponding to HW engines to be enabled. - * - Write mc_device_enable_r with the updated value. - * - Poll mc_device_enable_r to confirm register write success. - * - Release g->mc.enable_lock spinlock. - */ - int (*reset_engines_all)(struct gk20a *g, u32 devtype); -#ifdef CONFIG_NVGPU_HAL_NON_FUSA - void (*elpg_enable)(struct gk20a *g); -#endif - bool (*intr_get_unit_info)(struct gk20a *g, u32 unit); - -#endif /* NVGPU_NEXT_GOPS_MC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h deleted file mode 100644 index 348763f02..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_pbdma.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_PBDMA_H -#define NVGPU_NEXT_GOPS_PBDMA_H - - /* Leave extra tab to fit into gops_pbdma structure */ - - u32 (*set_channel_info_chid)(u32 chid); - u32 (*set_intr_notify)(u32 eng_intr_vector); - u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id); - void (*pbdma_force_ce_split)(struct gk20a *g); - u32 (*get_num_of_pbdmas)(void); - -#endif /* NVGPU_NEXT_GOPS_PBDMA_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h deleted file mode 100644 index 890e275d6..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_perf.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_PERF_H -#define NVGPU_NEXT_GOPS_PERF_H - - /* Leave extra tab to fit into gops_fifo structure */ - void (*enable_hs_streaming)(struct gk20a *g, bool enable); - void (*reset_hs_streaming_credits)(struct gk20a *g); - void (*enable_pmasys_legacy_mode)(struct gk20a *g, bool enable); - -#endif /* NVGPU_NEXT_GOPS_PERF_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h deleted file mode 100644 index 2d85305dc..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_priv_ring.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_PRIV_RING_H -#define NVGPU_NEXT_GOPS_PRIV_RING_H - - /* Leave extra tab to fit into gops_ce structure */ -#ifdef CONFIG_NVGPU_MIG - int (*config_gr_remap_window)(struct gk20a *g, u32 gr_syspipe_indx, - bool enable); - int (*config_gpc_rs_map)(struct gk20a *g, bool enable); -#endif - -#endif /* NVGPU_NEXT_GOPS_PRIV_RING_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h deleted file mode 100644 index d25e2d826..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_runlist.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NEXT_GOPS_RUNLIST_H -#define NVGPU_NEXT_GOPS_RUNLIST_H - - /* Leave extra tab to fit into gops_runlist structure */ - - u32 (*get_runlist_id)(struct gk20a *g, u32 runlist_pri_base); - u32 (*get_engine_id_from_rleng_id)(struct gk20a *g, - u32 rleng_id, u32 runlist_pri_base); - u32 (*get_chram_bar0_offset)(struct gk20a *g, u32 runlist_pri_base); - void (*get_pbdma_info)(struct gk20a *g, u32 runlist_pri_base, - struct nvgpu_next_pbdma_info *pbdma_info); - u32 (*get_engine_intr_id)(struct gk20a *g, u32 runlist_pri_base, - u32 rleng_id); - u32 (*get_esched_fb_thread_id)(struct gk20a *g, u32 runlist_pri_base); - -#endif /* NVGPU_NEXT_GOPS_RUNLIST_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h deleted file mode 100644 index 38b31a861..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_litter.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_LITTER_H -#define NVGPU_NEXT_LITTER_H - -/* - * Litter constants. - * These should be in sync with GPU_LIT_* constants defined in nvgpu/gk20a.h. - */ -#define GPU_LIT_ROP_IN_GPC_BASE 52 -#define GPU_LIT_ROP_IN_GPC_SHARED_BASE 53 -#define GPU_LIT_ROP_IN_GPC_PRI_SHARED_IDX 54 -#define GPU_LIT_ROP_IN_GPC_STRIDE 55 - - -#endif /* NVGPU_NEXT_LITTER_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h deleted file mode 100644 index 63b7875d8..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mc.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_MC_H -#define NVGPU_NEXT_MC_H - -/** - * @file - * - * Declare intr specific struct. - */ -#include -#include - -struct nvgpu_intr_unit_info { - /** - * top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1 - * top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3 - * top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5 - * top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7 - */ - /** - * h/w defined vectorids for the s/w defined intr unit. - * Upto 32 vectorids (32 bits of a leaf register) are supported for - * the intr units that support multiple vector ids. - */ - u32 vectorid[NVGPU_CIC_INTR_VECTORID_SIZE_MAX]; - /** number of vectorid supported by the intr unit */ - u32 vectorid_size; - u32 subtree; /** subtree number corresponding to vectorid */ - u64 subtree_mask; /** leaf1_leaf0 value for the intr unit */ - /** - * This flag will be set to true after all the fields - * of nvgpu_intr_unit_info are configured. - */ - bool valid; -}; - -struct nvgpu_next_mc { - /** - * intr info array indexed by s/w defined intr unit name - */ - struct nvgpu_intr_unit_info intr_unit_info[NVGPU_CIC_INTR_UNIT_MAX]; - /** - * Leaf mask per subtree. Subtree is a pair of leaf registers. - * Each subtree corresponds to a bit in intr_top register. - */ - u64 subtree_mask_restore[HOST2SOC_NUM_SUBTREE]; -}; -#endif /* NVGPU_NEXT_MC_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h deleted file mode 100644 index 4a6bd9f66..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_mm.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_MM_H -#define NVGPU_NEXT_MM_H - - /** VAB struct */ - struct nvgpu_vab vab; - -#endif /* NVGPU_NEXT_MM_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h deleted file mode 100644 index c04859c28..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_netlist.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_NETLIST_H -#define NVGPU_NEXT_NETLIST_H - -/** - * @file - * - */ -#include - -struct gk20a; -struct nvgpu_netlist_vars; -struct netlist_av_list; - -bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code); -void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g); - -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list( - struct gk20a *g); -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list( - struct gk20a *g); -#ifdef CONFIG_NVGPU_GRAPHICS -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list( - struct gk20a *g); -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list( - struct gk20a *g); -#endif /* CONFIG_NVGPU_GRAPHICS */ - -#ifdef CONFIG_NVGPU_DEBUGGER -bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code); -void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g); - -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs( - struct gk20a *g); -#ifdef CONFIG_NVGPU_GRAPHICS -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs( - struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs( - struct gk20a *g); -#endif /* CONFIG_NVGPU_GRAPHICS */ -u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g); -void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g); -#endif /* CONFIG_NVGPU_DEBUGGER */ - -#endif /* NVGPU_NEXT_NETLIST_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h deleted file mode 100644 index 9303b8c40..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_pbdma.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_PBDMA_H -#define NVGPU_NEXT_PBDMA_H - -/** - * @file - * - * Declare pbdma specific struct and defines. - */ -#include - -#define PBDMA_PER_RUNLIST_SIZE 2U -#define NVGPU_INVALID_PBDMA_PRI_BASE U32_MAX -#define NVGPU_INVALID_PBDMA_ID U32_MAX - -struct nvgpu_next_pbdma_info { - /** The pri offset of the i'th PBDMA for runlist_pri_base */ - u32 pbdma_pri_base[PBDMA_PER_RUNLIST_SIZE]; - /** The ID of the i'th PBDMA that runs channels on this runlist */ - u32 pbdma_id[PBDMA_PER_RUNLIST_SIZE]; -}; - -#endif /* NVGPU_NEXT_PBDMA_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h deleted file mode 100644 index 96abe038d..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_runlist.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_NEXT_RUNLIST_H -#define NVGPU_NEXT_RUNLIST_H - -/** - * @file - * - * Declare runlist info specific struct and defines. - */ -#include - -struct nvgpu_next_pbdma_info; -struct nvgpu_device; -struct nvgpu_fifo; - -#define RLENG_PER_RUNLIST_SIZE 3 - -struct nvgpu_next_runlist { - /** Runlist pri base - offset into device's runlist space */ - u32 runlist_pri_base; - /** Channel ram address in bar0 pri space */ - u32 chram_bar0_offset; - /** Pointer to pbdma info stored in engine_info*/ - const struct nvgpu_next_pbdma_info *pbdma_info; - /** Pointer to engine info for per runlist engine id */ - const struct nvgpu_device *rl_dev_list[RLENG_PER_RUNLIST_SIZE]; -}; - -void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f); - -#endif /* NVGPU_NEXT_RUNLIST_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h deleted file mode 100644 index c850bd0e8..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_sim.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_SIM_NEXT_H -#define NVGPU_SIM_NEXT_H - -#include - -#ifdef CONFIG_NVGPU_SIM - -struct gk20a; - -void nvgpu_next_init_sim_support(struct gk20a *g); - -#endif - -#ifdef CONFIG_NVGPU_DEBUGGER -int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g); -void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g); -#endif /* CONFIG_NVGPU_DEBUGGER */ - -int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g); -void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g); -#endif /* NVGPU_SIM_NEXT_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h index 5cf2a6415..e780ce3b7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h @@ -23,6 +23,8 @@ #ifndef NVGPU_PBDMA_COMMON_H #define NVGPU_PBDMA_COMMON_H +#include + /** * @file * @@ -36,7 +38,16 @@ struct gk20a; /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) -#include "include/nvgpu/nvgpu_next_pbdma.h" +#define PBDMA_PER_RUNLIST_SIZE 2U +#define NVGPU_INVALID_PBDMA_PRI_BASE U32_MAX +#define NVGPU_INVALID_PBDMA_ID U32_MAX + +struct nvgpu_next_pbdma_info { + /** The pri offset of the i'th PBDMA for runlist_pri_base */ + u32 pbdma_pri_base[PBDMA_PER_RUNLIST_SIZE]; + /** The ID of the i'th PBDMA that runs channels on this runlist */ + u32 pbdma_id[PBDMA_PER_RUNLIST_SIZE]; +}; #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/profiler.h b/drivers/gpu/nvgpu/include/nvgpu/profiler.h index de9bc6886..78a89f4a0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/profiler.h +++ b/drivers/gpu/nvgpu/include/nvgpu/profiler.h @@ -184,5 +184,9 @@ void nvgpu_profiler_free_pma_stream(struct nvgpu_profiler_object *prof); bool nvgpu_profiler_validate_regops_allowlist(struct nvgpu_profiler_object *prof, u32 offset, enum nvgpu_pm_resource_hwpm_register_type *type); +#ifdef CONFIG_NVGPU_HAL_NON_FUSA +void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g); +#endif /* CONFIG_NVGPU_HAL_NON_FUSA */ + #endif /* CONFIG_NVGPU_PROFILER */ #endif /* NVGPU_PROFILER_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/runlist.h index c6b8a179d..b524309d5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/runlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/runlist.h @@ -33,17 +33,19 @@ * Runlist interface. */ -/** @cond DOXYGEN_SHOULD_SKIP_THIS */ -#if defined(CONFIG_NVGPU_NON_FUSA) -#include -#endif -/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ - struct gk20a; struct nvgpu_tsg; struct nvgpu_fifo; struct nvgpu_channel; +/** @cond DOXYGEN_SHOULD_SKIP_THIS */ +#if defined(CONFIG_NVGPU_NON_FUSA) +struct nvgpu_next_pbdma_info; +struct nvgpu_device; + +#define RLENG_PER_RUNLIST_SIZE 3 +#endif + /** * Low interleave level for runlist entry. TSGs with this interleave level * typically appear only once in the runlist. @@ -79,6 +81,22 @@ struct nvgpu_channel; /** Runlist identifier is invalid. */ #define NVGPU_INVALID_RUNLIST_ID U32_MAX +/** @cond DOXYGEN_SHOULD_SKIP_THIS */ +#if defined(CONFIG_NVGPU_NON_FUSA) +struct nvgpu_next_runlist { + /* Ampere+ runlist info additions */ + + /** Runlist pri base - offset into device's runlist space */ + u32 runlist_pri_base; + /** Channel ram address in bar0 pri space */ + u32 chram_bar0_offset; + /** Pointer to pbdma info stored in engine_info*/ + const struct nvgpu_next_pbdma_info *pbdma_info; + /** Pointer to engine info for per runlist engine id */ + const struct nvgpu_device *rl_dev_list[RLENG_PER_RUNLIST_SIZE]; +}; +#endif + struct nvgpu_runlist { /** Runlist identifier. */ u32 id; @@ -103,7 +121,7 @@ struct nvgpu_runlist { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) - /* nvgpu next runlist info additions */ + /* Ampere+ runlist info additions */ struct nvgpu_next_runlist nvgpu_next; #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ @@ -363,6 +381,11 @@ u32 nvgpu_runlist_get_runlists_mask(struct gk20a *g, u32 id, * Walks through all active engines info, and initialize runlist info. */ void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f); + +#if defined(CONFIG_NVGPU_NON_FUSA) +void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f); +#endif + /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #define rl_dbg(g, fmt, arg...) \ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sim.h b/drivers/gpu/nvgpu/include/nvgpu/sim.h index 8737bcb75..a82d1d32a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sim.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sim.h @@ -24,13 +24,9 @@ #ifdef CONFIG_NVGPU_SIM +#include #include #include -/** @cond DOXYGEN_SHOULD_SKIP_THIS */ -#if defined(CONFIG_NVGPU_NON_FUSA) -#include -#endif -/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /* * Size of SIM ring buffers. @@ -108,5 +104,20 @@ static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); } +/** @cond DOXYGEN_SHOULD_SKIP_THIS */ +#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) +void nvgpu_next_init_sim_support(struct gk20a *g); + +#ifdef CONFIG_NVGPU_DEBUGGER +int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g); +void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g); +#endif /* CONFIG_NVGPU_DEBUGGER */ + +int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g); +void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g); + +#endif +/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ + #endif #endif /* NVGPU_SIM_H */ diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_prof.c b/drivers/gpu/nvgpu/os/linux/ioctl_prof.c index 182211ed8..a2d16654f 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_prof.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_prof.c @@ -39,12 +39,6 @@ #include "ioctl_tsg.h" #include "ioctl.h" -/** @cond DOXYGEN_SHOULD_SKIP_THIS */ -#if defined(CONFIG_NVGPU_NON_FUSA) -#include "os/linux/nvgpu_next_ioctl_prof.h" -#endif -/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ - #include #include #include @@ -762,6 +756,78 @@ static int nvgpu_prof_ioctl_pma_stream_update_get_put(struct nvgpu_profiler_obje return 0; } +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +static u32 nvgpu_prof_vab_reserve_translate_vab_mode(struct gk20a *g, u32 mode) +{ + u32 vab_mode = 0U; + + if (mode == NVGPU_PROFILER_VAB_RANGE_CHECKER_MODE_ACCESS) { + vab_mode = NVGPU_VAB_MODE_ACCESS; + } else if (mode == NVGPU_PROFILER_VAB_RANGE_CHECKER_MODE_DIRTY) { + vab_mode = NVGPU_VAB_MODE_DIRTY; + } else { + nvgpu_err(g, "Unknown vab mode: 0x%x", mode); + } + + return vab_mode; +} + +static int nvgpu_prof_ioctl_vab_reserve(struct nvgpu_profiler_object *prof, + struct nvgpu_profiler_vab_reserve_args *arg) +{ + struct gk20a *g = prof->g; + int err; + u32 vab_mode = nvgpu_prof_vab_reserve_translate_vab_mode(g, + (u32)arg->vab_mode); + struct nvgpu_profiler_vab_range_checker *user_ckr = + (struct nvgpu_profiler_vab_range_checker *)(uintptr_t) + arg->range_checkers_ptr; + struct nvgpu_vab_range_checker *ckr; + + if (arg->num_range_checkers == 0) { + nvgpu_err(g, "Range checkers cannot be zero"); + return -EINVAL; + } + + ckr = nvgpu_kzalloc(g, sizeof(struct nvgpu_vab_range_checker) * + arg->num_range_checkers); + if (copy_from_user(ckr, user_ckr, + sizeof(struct nvgpu_vab_range_checker) * + arg->num_range_checkers)) { + return -EFAULT; + } + + err = g->ops.fb.vab.reserve(g, vab_mode, arg->num_range_checkers, ckr); + + nvgpu_kfree(g, ckr); + + return err; +} + +static int nvgpu_prof_ioctl_vab_flush(struct nvgpu_profiler_object *prof, + struct nvgpu_profiler_vab_flush_state_args *arg) +{ + int err; + struct gk20a *g = prof->g; + u64 *user_data = nvgpu_kzalloc(g, arg->buffer_size); + + err = g->ops.fb.vab.dump_and_clear(g, user_data, arg->buffer_size); + if (err < 0) { + goto fail; + } + + if (copy_to_user((void __user *)(uintptr_t)arg->buffer_ptr, + user_data, arg->buffer_size)) { + nvgpu_err(g, "copy_to_user failed!"); + err = -EFAULT; + } + +fail: + nvgpu_kfree(g, user_data); + return err; +} +#endif + long nvgpu_prof_fops_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { @@ -848,13 +914,35 @@ long nvgpu_prof_fops_ioctl(struct file *filp, unsigned int cmd, (struct nvgpu_profiler_pma_stream_update_get_put_args *)buf); break; - default: #if defined(CONFIG_NVGPU_NON_FUSA) - err = nvgpu_next_prof_fops_ioctl(prof, cmd, (void *)buf); -#else + case NVGPU_PROFILER_IOCTL_VAB_RESERVE: + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) { + break; + } + + err = nvgpu_prof_ioctl_vab_reserve(prof, + (struct nvgpu_profiler_vab_reserve_args *)buf); + break; + + case NVGPU_PROFILER_IOCTL_VAB_FLUSH_STATE: + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) { + break; + } + + err = nvgpu_prof_ioctl_vab_flush(prof, + (struct nvgpu_profiler_vab_flush_state_args *)buf); + break; + + case NVGPU_PROFILER_IOCTL_VAB_RELEASE: + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) { + err = g->ops.fb.vab.release(g); + } + break; +#endif + + default: nvgpu_err(g, "unrecognized profiler ioctl cmd: 0x%x", cmd); err = -ENOTTY; -#endif break; } @@ -869,3 +957,4 @@ long nvgpu_prof_fops_ioctl(struct file *filp, unsigned int cmd, return err; } + diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_prof.h b/drivers/gpu/nvgpu/os/linux/ioctl_prof.h index 8180f9db6..596a7a3bd 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_prof.h +++ b/drivers/gpu/nvgpu/os/linux/ioctl_prof.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,10 +20,18 @@ struct inode; struct file; +#if defined(CONFIG_NVGPU_NON_FUSA) +struct nvgpu_profiler_object; +#endif int nvgpu_prof_dev_fops_open(struct inode *inode, struct file *filp); int nvgpu_prof_ctx_fops_open(struct inode *inode, struct file *filp); int nvgpu_prof_fops_release(struct inode *inode, struct file *filp); long nvgpu_prof_fops_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); +#if defined(CONFIG_NVGPU_NON_FUSA) +int nvgpu_next_prof_fops_ioctl(struct nvgpu_profiler_object *prof, + unsigned int cmd, void *buf); +#endif + #endif /* LINUX_IOCTL_PROF_H */ diff --git a/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c b/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c deleted file mode 100644 index 4f52ecdcb..000000000 --- a/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * GA10B Tegra Platform Interface - * - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include "nvgpu_next_ioctl_prof.h" - -static u32 nvgpu_prof_vab_reserve_translate_vab_mode(struct gk20a *g, u32 mode) -{ - u32 vab_mode = 0U; - - if (mode == NVGPU_PROFILER_VAB_RANGE_CHECKER_MODE_ACCESS) { - vab_mode = NVGPU_VAB_MODE_ACCESS; - } else if (mode == NVGPU_PROFILER_VAB_RANGE_CHECKER_MODE_DIRTY) { - vab_mode = NVGPU_VAB_MODE_DIRTY; - } else { - nvgpu_err(g, "Unknown vab mode: 0x%x", mode); - } - - return vab_mode; -} - -static int nvgpu_prof_ioctl_vab_reserve(struct nvgpu_profiler_object *prof, - struct nvgpu_profiler_vab_reserve_args *arg) -{ - struct gk20a *g = prof->g; - int err; - u32 vab_mode = nvgpu_prof_vab_reserve_translate_vab_mode(g, - (u32)arg->vab_mode); - struct nvgpu_profiler_vab_range_checker *user_ckr = - (struct nvgpu_profiler_vab_range_checker *)(uintptr_t) - arg->range_checkers_ptr; - struct nvgpu_vab_range_checker *ckr; - - if (arg->num_range_checkers == 0) { - nvgpu_err(g, "Range checkers cannot be zero"); - return -EINVAL; - } - - ckr = nvgpu_kzalloc(g, sizeof(struct nvgpu_vab_range_checker) * - arg->num_range_checkers); - if (copy_from_user(ckr, user_ckr, - sizeof(struct nvgpu_vab_range_checker) * - arg->num_range_checkers)) { - return -EFAULT; - } - - err = g->ops.fb.vab.reserve(g, vab_mode, arg->num_range_checkers, ckr); - - nvgpu_kfree(g, ckr); - - return err; -} - -static int nvgpu_prof_ioctl_vab_flush(struct nvgpu_profiler_object *prof, - struct nvgpu_profiler_vab_flush_state_args *arg) -{ - int err; - struct gk20a *g = prof->g; - u64 *user_data = nvgpu_kzalloc(g, arg->buffer_size); - - err = g->ops.fb.vab.dump_and_clear(g, user_data, arg->buffer_size); - if (err < 0) { - goto fail; - } - - if (copy_to_user((void __user *)(uintptr_t)arg->buffer_ptr, - user_data, arg->buffer_size)) { - nvgpu_err(g, "copy_to_user failed!"); - err = -EFAULT; - } - -fail: - nvgpu_kfree(g, user_data); - return err; -} - -int nvgpu_next_prof_fops_ioctl(struct nvgpu_profiler_object *prof, - unsigned int cmd, void *buf) -{ - int err = -ENOTTY; - struct gk20a *g = prof->g; - - switch (cmd) { - case NVGPU_PROFILER_IOCTL_VAB_RESERVE: - if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) { - break; - } - - err = nvgpu_prof_ioctl_vab_reserve(prof, - (struct nvgpu_profiler_vab_reserve_args *)buf); - break; - - case NVGPU_PROFILER_IOCTL_VAB_FLUSH_STATE: - if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) { - break; - } - - err = nvgpu_prof_ioctl_vab_flush(prof, - (struct nvgpu_profiler_vab_flush_state_args *)buf); - break; - - case NVGPU_PROFILER_IOCTL_VAB_RELEASE: - if (nvgpu_is_enabled(g, NVGPU_SUPPORT_VAB_ENABLED)) { - err = g->ops.fb.vab.release(g); - } - break; - - default: - nvgpu_err(g, "unrecognized profiler ioctl cmd: 0x%x", cmd); - err = -ENOTTY; - break; - } - return err; -} diff --git a/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h b/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h deleted file mode 100644 index 52e08ce05..000000000 --- a/drivers/gpu/nvgpu/os/linux/nvgpu_next_ioctl_prof.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef LINUX_NVGPU_NEXT_IOCTL_PROF_H -#define LINUX_NVGPU_NEXT_IOCTL_PROF_H - -struct nvgpu_profiler_object; - -int nvgpu_next_prof_fops_ioctl(struct nvgpu_profiler_object *prof, - unsigned int cmd, void *buf); - -#endif /* LINUX_NVGPU_NEXT_IOCTL_PROF_H */