From fa439d34d1de79569a994a514a9b70cd084f7f50 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 9 May 2019 17:32:23 +0530 Subject: [PATCH] gpu: nvgpu: fix MISRA 10.3 violation in hal.gr.config unit Below MISRA 10.3 violation is reported in hal.gr.config unit Error: MISRA C-2012 Rule 10.3: nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:150: misra_violation: Implicit conversion of "(int)average_tpcs - scale_factor * num_tpc_gpc[gpc_id]" from essential type "unsigned 32-bit int" to different or narrower essential type "signed 32-bit int". Fix this by converting "diff" variable to u32 and checking for greater value before doing subtraction operation Jira NVGPU-3406 Change-Id: I27695db5bd3a4f20db878888dc87dc78ff04888a Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2115590 GVS: Gerrit_Virtual_Submit Reviewed-by: Philip Elcan Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c index 31812552a..133c1e233 100644 --- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c +++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c @@ -53,7 +53,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, u32 scg_world_perf; u32 gpc_id; u32 pes_id; - int diff; + u32 diff; bool is_tpc_removed_gpc = false; bool is_tpc_removed_pes = false; u32 max_tpc_gpc = 0U; @@ -147,11 +147,14 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, for (gpc_id =0; gpc_id < nvgpu_gr_config_get_gpc_count(gr_config); gpc_id++) { - diff = average_tpcs - scale_factor * num_tpc_gpc[gpc_id]; - if (diff < 0) { - diff = -diff; + if (average_tpcs > (scale_factor * num_tpc_gpc[gpc_id])) { + diff = average_tpcs - + (scale_factor * num_tpc_gpc[gpc_id]); + } else { + diff = (scale_factor * num_tpc_gpc[gpc_id]) - + average_tpcs; } - deviation += U32(diff); + deviation += diff; } deviation /= nvgpu_gr_config_get_gpc_count(gr_config);