From fa6ada7619d1c4a0bdcd7c1fc684155443932a2b Mon Sep 17 00:00:00 2001 From: Rajesh Devaraj Date: Mon, 29 Jul 2019 14:44:32 +0530 Subject: [PATCH] gpu: nvgpu: disable hw error injection support in safety-release This patch disables HW based fake error injection support in safety-release build. For this purpose, it makes use of the following flag: CONFIG_NVGPU_INJECT_HWERR. JIRA NVGPU-3861 Change-Id: I1fa8544e67adbc53a1f3b98b340d76cf4f5bf524 Signed-off-by: Rajesh Devaraj Reviewed-on: https://git-master.nvidia.com/r/2163289 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.shared.configs | 2 ++ drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c | 2 ++ drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 8 ++++++++ drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c | 2 ++ drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c | 2 ++ 7 files changed, 19 insertions(+) diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 3d43c3f9c..a7176f616 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -50,6 +50,7 @@ ccflags-y += -DCONFIG_NVGPU_FALCON_DEBUG ccflags-y += -DCONFIG_NVGPU_FALCON_NON_FUSA ccflags-y += -DCONFIG_NVGPU_IOCTL_NON_FUSA ccflags-y += -DCONFIG_NVGPU_COMMON_NON_FUSA +ccflags-y += -DCONFIG_NVGPU_INJECT_HWERR ifeq ($(CONFIG_NVGPU_LOGGING),y) ccflags-y += -DCONFIG_NVGPU_LOGGING=1 diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index 6fbdbbaec..8e9b43179 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -106,6 +106,8 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SYSFS NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_FALCON_DEBUG +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_INJECT_HWERR + # # Flags enabled only for regular build profile. # diff --git a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c index 2aaef9686..f0512e59c 100644 --- a/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c @@ -31,6 +31,7 @@ #include +#ifdef CONFIG_NVGPU_INJECT_HWERR int gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g, struct nvgpu_hw_err_inject_info *err, u32 error_info) @@ -100,6 +101,7 @@ gv11b_fb_intr_get_hubmmu_err_desc(struct gk20a *g) return &hubmmu_err_desc; } +#endif /* CONFIG_NVGPU_INJECT_HWERR */ static void gv11b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status) { diff --git a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c index 9a75b8a92..7f7098b4d 100644 --- a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c @@ -28,6 +28,7 @@ #include "ecc_gv11b.h" +#ifdef CONFIG_NVGPU_INJECT_HWERR int gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g, struct nvgpu_hw_err_inject_info *err, u32 error_info) { @@ -333,6 +334,7 @@ gv11b_gr_intr_get_gcc_err_desc(struct gk20a *g) return &gcc_err_desc; } +#endif /* CONFIG_NVGPU_INJECT_HWERR */ static void gv11b_ecc_enable_smlrf(struct gk20a *g, u32 fecs_feature_override_ecc, bool opt_ecc_en) diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 2bb5ab974..c6151d6ed 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -185,8 +185,10 @@ static void gv11b_init_gpu_characteristics(struct gk20a *g) static const struct gpu_ops gv11b_ops = { .ltc = { +#ifdef CONFIG_NVGPU_INJECT_HWERR .get_ltc_err_desc = gv11b_ltc_get_err_desc, +#endif /* CONFIG_NVGPU_INJECT_HWERR */ .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, .init_fs_state = gv11b_ltc_init_fs_state, .flush = gm20b_flush_ltc, @@ -290,6 +292,7 @@ static const struct gpu_ops gv11b_ops = { .ecc = { .detect = gv11b_ecc_detect_enabled_units, .init = gv11b_ecc_init, +#ifdef CONFIG_NVGPU_INJECT_HWERR .get_mmu_err_desc = gv11b_gr_intr_get_mmu_err_desc, .get_gcc_err_desc = @@ -300,6 +303,7 @@ static const struct gpu_ops gv11b_ops = { gv11b_gr_intr_get_gpccs_err_desc, .get_fecs_err_desc = gv11b_gr_intr_get_fecs_err_desc, +#endif /* CONFIG_NVGPU_INJECT_HWERR */ }, .ctxsw_prog = { .hw_get_fecs_header_size = @@ -705,8 +709,10 @@ static const struct gpu_ops gv11b_ops = { .is_valid_compute = gv11b_class_is_valid_compute, }, .fb = { +#ifdef CONFIG_NVGPU_INJECT_HWERR .get_hubmmu_err_desc = gv11b_fb_intr_get_hubmmu_err_desc, +#endif /* CONFIG_NVGPU_INJECT_HWERR */ .init_hw = gv11b_fb_init_hw, .init_fs_state = gv11b_fb_init_fs_state, .set_mmu_page_size = NULL, @@ -1076,8 +1082,10 @@ static const struct gpu_ops gv11b_ops = { .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, }, .pmu = { +#ifdef CONFIG_NVGPU_INJECT_HWERR .get_pmu_err_desc = gv11b_pmu_intr_get_err_desc, +#endif /* CONFIG_NVGPU_INJECT_HWERR */ /* * Basic init ops are must, as PMU engine used by ACR to * load & bootstrap GR LS falcons without LS PMU, remaining diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c index dd5ba0318..84c621c3b 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c @@ -34,6 +34,7 @@ #include +#ifdef CONFIG_NVGPU_INJECT_HWERR int gv11b_ltc_inject_ecc_error(struct gk20a *g, struct nvgpu_hw_err_inject_info *err, u32 error_info) { @@ -89,6 +90,7 @@ struct nvgpu_hw_err_inject_info_desc * gv11b_ltc_get_err_desc(struct gk20a *g) return <c_err_desc; } +#endif /* CONFIG_NVGPU_INJECT_HWERR */ /* * Sets the ZBC stencil for the passed index. diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c index ea5480b09..b56ba60e5 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c @@ -39,6 +39,7 @@ #define ALIGN_4KB 12 +#ifdef CONFIG_NVGPU_INJECT_HWERR int gv11b_pmu_inject_ecc_error(struct gk20a *g, struct nvgpu_hw_err_inject_info *err, u32 error_info) { @@ -86,6 +87,7 @@ gv11b_pmu_intr_get_err_desc(struct gk20a *g) return &pmu_err_desc; } +#endif /* CONFIG_NVGPU_INJECT_HWERR */ /* error handler */ void gv11b_clear_pmu_bar0_host_err_status(struct gk20a *g)