diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index d8aad8271..6fab1c11d 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -420,15 +420,14 @@ sync: therm_fusa: safe: yes owner: Seshendra G - sources: [ hal/therm/therm_gm20b_fusa.c, - hal/therm/therm_gm20b.h, - hal/therm/therm_gv11b_fusa.c, + sources: [ hal/therm/therm_gv11b_fusa.c, hal/therm/therm_gv11b.h ] therm: safe: no owner: Seshendra G sources: [ hal/therm/therm_gm20b.c, + hal/therm/therm_gm20b.h, hal/therm/therm_tu104.c, hal/therm/therm_tu104.h, hal/therm/therm_gp10b.c, diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 480062f41..7f131403c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -654,7 +654,6 @@ nvgpu-y += \ hal/ptimer/ptimer_gk20a_fusa.o \ hal/ptimer/ptimer_gp10b.o \ hal/sync/syncpt_cmdbuf_gv11b_fusa.o \ - hal/therm/therm_gm20b_fusa.o \ hal/therm/therm_gv11b_fusa.o \ hal/top/top_gm20b_fusa.o \ hal/top/top_gp10b_fusa.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 59e41228b..c6b7141cc 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -237,7 +237,6 @@ srcs += hal/mm/mm_gv11b_fusa.c \ hal/priv_ring/priv_ring_gp10b_fusa.c \ hal/ptimer/ptimer_gk20a_fusa.c \ hal/sync/syncpt_cmdbuf_gv11b_fusa.c \ - hal/therm/therm_gm20b_fusa.c \ hal/therm/therm_gv11b_fusa.c \ hal/top/top_gm20b_fusa.c \ hal/top/top_gp10b_fusa.c \ diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index a6472b15d..d44e903d0 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1156,7 +1156,9 @@ static const struct gpu_ops gv11b_ops = { .init_therm_support = nvgpu_init_therm_support, .init_therm_setup_hw = gv11b_init_therm_setup_hw, .init_elcg_mode = gv11b_therm_init_elcg_mode, +#ifdef CONFIG_NVGPU_NON_FUSA .init_blcg_mode = gm20b_therm_init_blcg_mode, +#endif .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, }, .pmu = { diff --git a/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c b/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c index 71edf794d..7c5f2e303 100644 --- a/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c +++ b/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c @@ -192,3 +192,39 @@ u32 gm20b_therm_idle_slowdown_disable(struct gk20a *g) return saved_val; } + +void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) +{ + u32 gate_ctrl; + bool error_status = false; + + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { + return; + } + + gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(engine)); + + switch (mode) { + case BLCG_RUN: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_blk_clk_m(), + therm_gate_ctrl_blk_clk_run_f()); + break; + case BLCG_AUTO: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_blk_clk_m(), + therm_gate_ctrl_blk_clk_auto_f()); + break; + default: + nvgpu_err(g, + "invalid blcg mode %d", mode); + error_status = true; + break; + } + + if (error_status == true) { + return; + } + + nvgpu_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); +} \ No newline at end of file diff --git a/drivers/gpu/nvgpu/hal/therm/therm_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/therm/therm_gm20b_fusa.c deleted file mode 100644 index 6b51142f0..000000000 --- a/drivers/gpu/nvgpu/hal/therm/therm_gm20b_fusa.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * GM20B THERMAL - * - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include - -#include "therm_gm20b.h" - -#include - -void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) -{ - u32 gate_ctrl; - bool error_status = false; - - if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { - return; - } - - gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(engine)); - - switch (mode) { - case BLCG_RUN: - gate_ctrl = set_field(gate_ctrl, - therm_gate_ctrl_blk_clk_m(), - therm_gate_ctrl_blk_clk_run_f()); - break; - case BLCG_AUTO: - gate_ctrl = set_field(gate_ctrl, - therm_gate_ctrl_blk_clk_m(), - therm_gate_ctrl_blk_clk_auto_f()); - break; - default: - nvgpu_err(g, - "invalid blcg mode %d", mode); - error_status = true; - break; - } - - if (error_status == true) { - return; - } - - nvgpu_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); -}