diff --git a/drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c b/drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c index ee0f83be9..85514c0a1 100644 --- a/drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c +++ b/drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c @@ -202,8 +202,8 @@ static int pmu_handle_event(struct nvgpu_pmu *pmu, struct pmu_msg *msg) } break; case PMU_UNIT_PG: - if (pmu->pg->process_rpc_event != NULL) { - err = pmu->pg->process_rpc_event(g, (void *)&msg->hdr); + if (pmu->pg->process_pg_event != NULL) { + err = pmu->pg->process_pg_event(g, (void *)&msg->hdr); } break; default: diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c index acb82bb5b..629e364b4 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -433,7 +433,7 @@ static int ga10b_pmu_pg_handle_idle_snap_rpc(struct gk20a *g, return err; } -static int ga10b_pmu_pg_process_rpc_event(struct gk20a *g, void *pmumsg) +static int ga10b_pmu_pg_process_pg_event(struct gk20a *g, void *pmumsg) { int err = 0; struct pmu_nv_rpc_struct_lpwr_pg_async_cmd_resp *async_cmd; @@ -483,5 +483,5 @@ void nvgpu_ga10b_pg_sw_init(struct gk20a *g, pg->hw_load_zbc = NULL; pg->rpc_handler = ga10b_pg_rpc_handler; pg->init_send = ga10b_pmu_pg_init_send; - pg->process_rpc_event = ga10b_pmu_pg_process_rpc_event; + pg->process_pg_event = ga10b_pmu_pg_process_pg_event; } diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gv11b.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gv11b.c index 57ba36b10..b26f428a5 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gv11b.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gv11b.c @@ -27,6 +27,7 @@ #include #include +#include "pmu_pg.h" #include "pg_sw_gv11b.h" #include "pg_sw_gp106.h" #include "pg_sw_gm20b.h" @@ -134,6 +135,30 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) return 0; } +static int gv11b_pmu_pg_process_pg_event(struct gk20a *g, void *pmumsg) +{ + int err = 0; + struct pmu_msg *msg = (struct pmu_msg *) pmumsg; + + switch (msg->msg.pg.async_cmd_resp.msg_id) { + case PMU_PG_MSG_ASYNC_CMD_DISALLOW: + if (msg->msg.pg.async_cmd_resp.ctrl_id == + PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + g->pmu->pg->disallow_state = PMU_ELPG_STAT_OFF; + } else { + nvgpu_err(g, "Invalid engine id"); + err = -EINVAL; + } + break; + default: + nvgpu_err(g, "Invalid message id: %d", + msg->msg.pg.async_cmd_resp.msg_id); + err = -EINVAL; + break; + } + return err; +} + void nvgpu_gv11b_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg) { @@ -153,4 +178,5 @@ void nvgpu_gv11b_pg_sw_init(struct gk20a *g, pg->hw_load_zbc = gm20b_pmu_pg_elpg_hw_load_zbc; pg->rpc_handler = NULL; pg->init_send = gm20b_pmu_pg_init_send; + pg->process_pg_event = gv11b_pmu_pg_process_pg_event; } diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c index acd0f8681..b13b883ba 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c @@ -402,7 +402,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) if ((BIT32(pg_engine_id) & pg_engine_id_list) != 0U) { if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { pmu->pg->elpg_stat = PMU_ELPG_STAT_OFF_PENDING; - if (pmu->pg->process_rpc_event != NULL) { + if (pmu->pg->process_pg_event != NULL) { pmu->pg->disallow_state = PMU_ELPG_STAT_OFF_PENDING; } @@ -453,7 +453,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) * Wait for DISALLOW_ACK RPC event from * PMU. */ - if (pmu->pg->process_rpc_event != NULL) { + if (pmu->pg->process_pg_event != NULL) { ptr = &pmu->pg->disallow_state; pmu_wait_message_cond(pmu, nvgpu_get_poll_timeout(g), diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h index 980658acd..55402e774 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -128,7 +128,7 @@ struct nvgpu_pmu_pg { void (*rpc_handler)(struct gk20a *g, struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc, struct rpc_handler_payload *rpc_payload); int (*init_send)(struct gk20a *g, struct nvgpu_pmu *pmu, u8 pg_engine_id); - int (*process_rpc_event)(struct gk20a *g, void *pmumsg); + int (*process_pg_event)(struct gk20a *g, void *pmumsg); }; /*PG defines used by nvpgu-pmu*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pg.h index eaea56cdc..f5b5102ac 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -117,12 +117,19 @@ struct pmu_pg_msg_eng_buf_stat { u8 status; }; +struct pmu_pg_msg_async_cmd_resp { + u8 msg_type; + u8 ctrl_id; + u8 msg_id; +}; + struct pmu_pg_msg { union { u8 msg_type; struct pmu_pg_msg_elpg_msg elpg_msg; struct pmu_pg_msg_stat stat; struct pmu_pg_msg_eng_buf_stat eng_buf_stat; + struct pmu_pg_msg_async_cmd_resp async_cmd_resp; /* TBD: other pg messages */ union pmu_ap_msg ap_msg; struct nv_pmu_rppg_msg rppg_msg;